Structure and method for realizing concurrent reading and concurrent writing of IP of synchronous dual-port memory

A memory and dual-port technology, which is applied to the structure and field of parallel read and write of synchronous dual-port memory IP, which can solve the problems of non-portability and increased system instability

Active Publication Date: 2010-07-07
EHIWAY MICROELECTRONIC SCI & TECH SUZHOU CO LTD
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  • Application Information

AI Technical Summary

Problems solved by technology

It increases the instability of the system and makes the design non-portable to different processes

Method used

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  • Structure and method for realizing concurrent reading and concurrent writing of IP of synchronous dual-port memory
  • Structure and method for realizing concurrent reading and concurrent writing of IP of synchronous dual-port memory
  • Structure and method for realizing concurrent reading and concurrent writing of IP of synchronous dual-port memory

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Embodiment Construction

[0043] The strategy proposed by the present invention has two key points: 1) selection and buffering of input signals; 2) selection of output data. These two key points are realized through input signal selection and cache strategy and output data selection strategy respectively.

[0044] image 3 Shows the structure of the dual-port memory system in the present invention, which includes: synchronous dual-port memory IP 300, arbitration circuit 301, readout control circuit 302, primary buffers 303 and 304, secondary buffers 303' and 304' , and selectors 305 and 306.

[0045] Wherein, the arbitration circuit 301, the L1 registers 303 and 304, and the selectors 305 and 306 mainly complete as Figure 4 The input signal selection and buffering strategy shown. The L1 buffer 303 and the selector 305 correspond to the A port, and operate on the input signal of the A port; the L1 buffer 304 and the selector 306 correspond to the B port, and operate on the B port input signal. It s...

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Abstract

The invention provides a synchronous dual-port memory IP based method for realizing the concurrent-read and concurrent-write operation. In the IP of the synchronous dual-port memory, when the reading and writing operation is performed on the same address at the same time, a reading and writing conflict at ports appears, so errors occur in the reading and writing operation. The method solves the problem of reading and writing conflict at the ports with a selective reading and writing control strategy and realizes the operation of reading original data in a memory first and then writing new data into the address in the same period. The method has the advantage of effectively solving the problem of reading and writing conflict at the ports of a dual-port memory; besides, a memory system withrelatively stable performance can be obtained by designing in the method; and the whole design can be realized by an automated tool, and the design is portable, so the development cycle of a product can be shortened.

Description

Background technique [0001] For a system with multiple processors, it needs to access the memory at the same time, which will cause serious data bus contention. And this can be avoided by adopting special structured memory, such as multi-port memory. Currently, multi-port memories, especially dual-port memories are widely used in data communication devices. [0002] For general synchronous dual-port memory intellectual property (Intellectual Property, referred to as IP), usually when the same address is read and written at the same time, it will cause errors in the read and write operations. The specific situation is as follows: When one port performs a read operation while another port performs a write operation on the address at the same time, the read data is wrong. The data read at this time can neither be guaranteed to be the original data on the address, nor can it be guaranteed to be the newly written data, but an uncertain value; when the two ports perform the read o...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F13/16G06F12/08G06F15/167G06F12/0884
Inventor 杨海钢蔡刚
Owner EHIWAY MICROELECTRONIC SCI & TECH SUZHOU CO LTD
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