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Image matrixing pretreatment method based on FPGA in high-resolution imaging system

An imaging system and high-resolution technology, applied in image memory management, image communication, electrical components, etc., can solve the problems of wasting on-chip RAM resources, low real-time performance of the system, and complicated boundary effect processing, etc., and achieve high real-time performance , the effect of easy handling

Inactive Publication Date: 2010-07-21
SHANGHAI MARITIME UNIVERSITY
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  • Claims
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Problems solved by technology

If you need to process an n*n image array, you need more than or equal to n RAMs or FIFOs as image data buffers, especially for processing high-resolution scanned images, which not only wastes a lot of valuable on-chip RAM resources of FPGA, and complicates the handling of boundary effects
Not only that, due to the need to store multiple rows of image data before processing, the real-time performance of the entire system is not high

Method used

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  • Image matrixing pretreatment method based on FPGA in high-resolution imaging system
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[0014] In order to make it easy to understand the technical means, creative features, purpose and effect of the present invention, the following combination figure 1 with figure 2 , the present invention will be described in detail in the example of preprocessing of bayer signal to RGB image signal in high-resolution scanning imaging.

[0015] In this scanning imaging system, the high-resolution bayer image signal of 2592*1944 needs to be preprocessed into RGB color signal, so the image data needs to be interpolated according to the 3*3 matrix. The 8-bit image signal is sent to the first shift register, and then stored into the first 4192-Byte-FIFO on the left from the FD (shift register) through a shift operation. After storing a row of image data, wait for the second row of image data When it is delivered, the image data of the second line is stored into the first FIFO (first-in-first-out memory) on the left from the FD through a shift operation, and at the same time, the ...

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Abstract

The invention discloses an image matrixing pretreatment method based on FPGA in a high-resolution imaging system, comprising the following steps: A. sending a first line of image data to a first FIFO RAM capable of storing the magnitude of one line of image data by the shifting function of n numbered shift registers; B. when a second line of data arrives, storing the second line of data into the first FIFO by n numbered FD in step A, and storing the first line of data into a second FIFO by the forward n-1 numbered FD of the first FIFO; and C. if the nth image data in the nth line reaches the first FD according to step B, respectively reading n-1 numbered data to the forward n-1 numbered FD thereof by the previous n-1 numbered FIFO, reading the FIFO and FD output ends to obtain an n*n image matrix, and processing by the required algorithm. The method can fully utilize the limited on-chip resource on FPGA as much as possible so as to simplify border effect treatment and cause instantaneity to be supreme.

Description

Technical field: [0001] The invention relates to a real-time image preprocessing method, in particular to an image matrix preprocessing method based on FPGA (Fied-Programmable Gage Array) in a high-resolution imaging system. Background technique: [0002] In a high-resolution scanning imaging system, FPGA-based image preprocessing will involve matrix operations (such as Bayer to RGB interpolation calculations), which will inevitably require a memory (internal or external) to temporarily store a few lines or the entire set. The frame image data is then processed by matrix multiplication. If you need to process an n*n image array, you need more than or equal to n RAMs or FIFOs as image data buffers, especially for processing high-resolution scanned images, which not only wastes a lot of valuable on-chip RAM resources of FPGA, It also complicates the handling of boundary effects. Not only that, the real-time performance of the whole system is not high due to the need to store...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H04N1/21G06T1/60
Inventor 潘胜达安博文
Owner SHANGHAI MARITIME UNIVERSITY
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