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Zero input bias current, auto-zeroed buffer for a sample and hold circuit

A technology of automatic zero adjustment and buffer, applied in the direction of DC coupled DC amplifier, electrical analog memory, electrical signal transmission system, etc., can solve problems such as current error

Inactive Publication Date: 2010-09-08
詹姆斯·加勒特
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

In some current-sensing applications, taking the current from the sampling capacitor may introduce unacceptable errors

Method used

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  • Zero input bias current, auto-zeroed buffer for a sample and hold circuit
  • Zero input bias current, auto-zeroed buffer for a sample and hold circuit
  • Zero input bias current, auto-zeroed buffer for a sample and hold circuit

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Embodiment Construction

[0014] figure 1 It is a fully differential circuit embodiment of the present invention. Note that the invention applies to single-ended configurations, eg only to BUFAs and single-input sample-and-hold modules (not shown). Sample and hold block 2 has differential inputs, one from BUFA and the other from BUFB. BUFA and BUFB are the same circuits that buffer Vin1 and Vin2 respectively.

[0015] as the picture shows, figure 1 Unity gain amplifiers 22 and 23 are included, Vin1 and Vin2 are respectively connected to their inputs, and these unity gain amplifiers output V'in1 and V'in2. These unity-gain amplifiers should exhibit 50mV or less of offset voltage to keep input bias current small.

[0016] Such as figure 1 Vin1 and Vin2 are shown to provide the same information for differential amplifiers 4 and 6, respectively, where a substantial amount of offset of amplifiers 4 and 6 is compensated.

[0017] P1 and P2 are switches, usually MOSFET transistors, which couple Vin1 and...

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PUM

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Abstract

An auto-zeroing, high impedance buffer for a sample and hold module that draws substantially no current from the input and has substantially no offset voltage at the output is discussed. During a hold mode, the offset voltage of an op-amp is accumulated on a capacitor. When the sample operation ensues the input signal is directed to the op-amp input via the capacitor where the circuitry is arranged so that the offset on the capacitor cancels the offset voltage of the op-amp. A second circuit may be fashioned and input to a sample and hold circuit for full differential operation.

Description

technical field [0001] The present invention relates to a buffer circuit that may be placed before a sample and hold circuit. Background technique [0002] Buffers that work with sample-and-hold circuits sometimes include a possibly automatic zeroing function. Auto-zeroing removes the DC offset that accompanies the signal of interest. In some prior art nulling methods, the input signal can be tied to a sampling capacitor and draw current from it. In some current-sensing applications, taking the current from the sampling capacitor may introduce unacceptable errors. [0003] Auto-zeroing is particularly useful where an operational amplifier may be part of a buffer and it has an offset voltage that can greatly affect the signal of interest. The offset voltage in an op amp can be of either polarity, and if the op amp circuit is configured with gain, the offset voltage is usually amplified along with the input signal. [0004] Eliminating or zeroing the offset voltage advanta...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H03M1/54H03F3/45
CPCG11C27/02G11C27/026
Inventor 詹姆斯·加勒特
Owner 詹姆斯·加勒特