Multi-die package and manufacturing method thereof

Abstract

The present invention discloses a multi-die package which facilitates heat dissipation for a high power consumption die. In the package, part of the lead frame is bent so as to be exposed at the surface of the package. On the opposite side of the exposed surface, a high power consumption die is attached. The other die with lower power consumption is not at the surface of the multi-die package.

Description

technical field [0001] The invention relates to an integrated circuit package, in particular to a multi-chip package favorable for heat dissipation. Background technique [0002] In offline applications of flyback converters, switching devices and control circuits tend to be fabricated in the same package to reduce system size and improve performance. However, switching devices generate more heat. In order to make the control circuit work reliably, the heat generated by the switching device must be dissipated in time. In other words, the package containing power devices and common devices must have good heat dissipation. [0003] figure 1 A traditional Small Outline Package (SOP) application is shown. In the package body 10 , the power chip 11 and the common chip 12 are fixed on the lead frame 16 . Connection and signal transmission are carried out between the chips and between the chips and the lead frame 16 through the leads 15 made on the pads 17 . The outer surface...

AI Technical Summary

Problems solved by technology

The heat dissipation of the encapsulation material 13 is usually not ideal, because the encapsulation material 13 is generally not a good heat conductor, not as good as metal.

In addition, the cross-sectional area of ​​the exposed pin 141 is too small, and the heat dissipation capability is not high.

In this packaging method, since the heat cannot be effectively dissipated, the power chip 11 will form a high-temperature junction and affect the reliability of the system.

In addition, the high temperature on the exposed pin 141 will also affect the connection strength between the exposed pin 141 and the printed circuit board

Images