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Preparation method of photolithographic alignment mark in nvm device preparation

A lithographic alignment and marking technology, applied in semiconductor/solid-state device manufacturing, optics, instruments, etc., can solve problems such as unusable, limited versatility, and difficult process realization

Active Publication Date: 2011-12-14
SHANGHAI HUAHONG GRACE SEMICON MFG CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

But this requirement is opposite to the process requirement of DCMP, so the process is very difficult to realize, and it cannot be used for some specific size designs, which also limits the versatility

Method used

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  • Preparation method of photolithographic alignment mark in nvm device preparation
  • Preparation method of photolithographic alignment mark in nvm device preparation
  • Preparation method of photolithographic alignment mark in nvm device preparation

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Embodiment Construction

[0019] NVM devices are usually composed of multiple semiconductor units that implement different functions, including memory cells (the memory cells include tunneling regions), high-voltage cells (usually thick gate oxide), medium-voltage cells or low-voltage cells, etc. (usually thinner gate oxide), therefore, it is necessary to prepare a plurality of gate oxide regions with different thicknesses in the preparation of the gate oxide. In the gate oxide preparation process, the thickest oxide layer is usually grown on the surface of the substrate first, and then the oxide layer at the predetermined position is sequentially etched away to the silicon substrate by photolithography in the order from the second thickest to the thinnest. , and re-grow gate oxide with a predetermined thickness. The subsequent process flow is generally as follows: after preparing gate oxide regions of various thicknesses according to requirements, deposit polysilicon on the entire surface, then use ga...

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Abstract

The invention discloses a preparation method of a photolithographic alignment mark in the preparation of an NVM device. The NVM device includes a tunneling layer and a plurality of gate oxide regions with different thicknesses. In the process of layer penetration and multiple gate oxide regions with different thicknesses, additional etching of photolithography alignment marks is added, so that the height of the finally formed steps can meet the requirements of the subsequent photolithography alignment process.

Description

technical field [0001] The invention relates to a method for preparing photolithographic alignment marks in the preparation of NVM devices. Background technique [0002] An NVM device is a commonly used memory device and is widely used. For devices below 0.18um that use STI structure isolation, the preparation process of the STI structure is simple: deposit a CMP barrier layer (usually SiN) on the substrate silicon wafer, and then define the position and position of the STI shallow trench by photolithography. The position of the active region, and then etch the STI shallow trench to form a shallow trench, then deposit silicon oxide on the substrate to fill the shallow trench, and then use the CMP process to planarize the substrate surface. Here During the process, a photolithography alignment mark is formed in the field area. In the preparation process of STI structures using CMP technology, there are generally two types: one is to use ordinary chemical mechanical polishin...

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G03F9/00H01L21/8246H10B20/00
Inventor 王雷
Owner SHANGHAI HUAHONG GRACE SEMICON MFG CORP