Method for realizing rear-end translation framework of heterogeneous multi-core virtual execution environment

A virtual execution, heterogeneous multi-core technology, applied in the direction of program control devices, etc., can solve problems such as incompatibility of results, incompatibility of programming models, and a large number of repeated work of programmers, so as to ensure compatibility and accelerate program execution.

Inactive Publication Date: 2011-01-05
SHANGHAI JIAO TONG UNIV
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Problems solved by technology

Due to the differences in the storage system of different hardware and the number of processor cores, as well as the incompatibility of different programming models, the compiled r

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  • Method for realizing rear-end translation framework of heterogeneous multi-core virtual execution environment
  • Method for realizing rear-end translation framework of heterogeneous multi-core virtual execution environment
  • Method for realizing rear-end translation framework of heterogeneous multi-core virtual execution environment

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Embodiment Construction

[0027] The method of the present invention is further described below: the present embodiment is implemented under the premise of the technical solution of the present invention, and detailed implementation and specific operation process are provided, but the protection scope of the present invention is not limited to the following examples .

[0028] In this embodiment, the back-end translation framework is implemented on the virtual execution environment GXBit based on the CPU / GPU heterogeneous multi-core architecture. As a virtual execution environment based on CPU / GPU heterogeneous multi-core architecture, the GXBit uses dynamic binary translation technology to provide a mapping strategy from the X86 instruction set to a specific GPU general-purpose computing programming environment. On GXBit, the parallelizable embedded loop part of the program and the corresponding loop information are extracted through binary instrumentation and analysis, and then the parallelized code ...

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Abstract

The invention relates to a method for realizing a rear-end translation framework of a heterogeneous multi-core virtual execution environment based on CPU-GPU (Central Processing Unit-Graphic Processing Unit) in the technical field of computers. The method comprises the following steps of: carrying out dynamic translation processing based on a basic block on binary codes so as to obtain a middle representation code; then, analyzing and labeling a cyclic border, a cyclic index and a temporary variable in the generated middle representation code; recognizing access operation in a program by filtering an LD (Laser Disc) and a storage instrument in the middle representation code, recognizing a variable type according to an input cycle information table, labeling the variable according to the corresponding variable type and recording the label in the middle representation code; separating a loop body from the labeled middle representation code through the judgment of a cyclic condition and the branch jump and extracting the operational part of the loop body; and finally, translating the middle representation code of the extracted operational part into a PTX (Performance Toolbox) code to realize the rear-end translation framework of the multi-core virtual execution environment. The invention is beneficial to promoting the wide application of the general operation of the GPU.

Description

technical field [0001] The present invention relates to an optimization method in the field of computer technology, in particular to a method realized by a back-end translation framework of a CPU-GPU-based heterogeneous multi-core virtual execution environment. Background technique [0002] Heterogeneous multi-core architectures are increasingly favored by high-performance computing, for example: Roadrunner, a supercomputer built by IBM for the US National Nuclear Safety Administration, is based on heterogeneous multi-core architectures. Roadrunner is built by AMD Opteron dual-core processor and PowerXcel18i processor, and its computing power has reached 1.026PetaFlops in 2008. Intel, AMD and NVDIA are also working on the development of multi-core heterogeneous chips, such as Fusion of CPU+GPU proposed by AMD, Tesla of NVIDIA and so on. [0003] The CPU / GPU heterogeneous multi-core architecture has developed particularly rapidly in recent years. The processing power and pr...

Claims

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Application Information

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IPC IPC(8): G06F9/44
Inventor 管海兵陈凯董国星肖汉波朱楠
Owner SHANGHAI JIAO TONG UNIV
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