Memory and method for manufacturing same

Abstract

The invention discloses a memory and a method for manufacturing the same. The method for manufacturing the memory comprises the following steps of: a memory polysilicon etching step for forming an etched memory polysilicon layer; and a grid polysilicon etching step for forming an etched grid polysilicon layer on the formed etched memory polysilicon layer and a word-line etching step for etching word lines on the formed etched grid polysilicon layer and removing polysilicon residues generated in the grid polysilicon etching step, wherein after the grid polysilicon etching step, the etched grid polysilicon layer is used for covering the etched memory polysilicon layer in three directions of an etched grid polysilicon layer plane. The method for manufacturing the memory not only can manufacture a memory and a PPS (Periods Per Second) capacitor at the same time, but also can avoid silicon substrate hollows generated by removing the grid polysilicon residues.

Description

technical field [0001] The invention relates to a method of manufacturing a memory, and a memory obtained by the method. Background technique [0002] In the process of manufacturing memory (specifically flash memory), the gate polysilicon, memory polysilicon and substrate that must be used in the flash memory process can be used to form a capacitor with a relatively large capacitance value that can be called a PPS capacitor , so that the PPS capacitor can be formed without an additional photomask (mask). Among them, the PPS capacitor refers to a three-layer stacked capacitor structure composed of two layers of polysilicon and a substrate, where PPS is the combination of gate polysilicon (Gate Poly), memory polysilicon (memory Poly) and substrate (Substrate). Abbreviation. [0003] However, when the memory is fabricated according to the above method, polysilicon residues in the form of polysilicon stringers are generated. Figure 1 to Figure 5 Various stages of a prior art...

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Problems solved by technology

However, although this gate polysilicon residue is removed in the subsequent word line etching step, due to the presence of gate polysilicon residue on the silicon dioxide (the trapezoidal region in the drawing indicates the silicon dioxide region), the upper and lower sides The gate polysilicon residue on the side is still on the substrate (such as a silicon substrate), so it will cause such as Figure 5 The recess of the silicon substrate is shown, which can be found especially in Figure 5 The recessed portion of the substrate in the upper right view of the

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