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Electrostatic discharge safeguard structure in integrated circuit

An electrostatic discharge protection and integrated circuit technology, applied in the direction of circuits, electrical components, and electric solid devices, can solve the problems of high trigger voltage, difficulty in design and realization, and large chip area of ​​thyristor devices, so as to reduce the trigger point voltage, The effect of improving uniform conduction and improving the ability to withstand electrostatic discharge current

Active Publication Date: 2012-02-22
BEIJING MXTRONICS CORP +1
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

With the reduction of the feature size of integrated circuits, CMOS devices need to occupy a large chip area as an electrostatic discharge protection device, and have the disadvantage of non-uniform conduction
As an electrostatic discharge protection device, a thyristor device has a high trigger voltage and may cause latch-up, which is difficult to design and implement.

Method used

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  • Electrostatic discharge safeguard structure in integrated circuit
  • Electrostatic discharge safeguard structure in integrated circuit
  • Electrostatic discharge safeguard structure in integrated circuit

Examples

Experimental program
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Embodiment Construction

[0037] The present invention will be described in detail below in conjunction with specific embodiments.

[0038] Such as figure 1 As shown, the input buffer is composed of PMOS transistor 105 and NMOS transistor 106 . The source of the PMOS transistor 105 is connected to the power rail 101 , and the source of the NMOS transistor 106 is connected to the ground rail 102 . The drains of the PMOS transistor 105 and the NMOS transistor 106 are connected to transmit signals into the chip. The gates of the PMOS transistor 105 and the NMOS transistor 106 are connected, and are connected to the input pad 103 through a resistor 114 . The output buffer is composed of a PMOS transistor 107 and an NMOS transistor 108 . The source of the PMOS transistor 107 is connected to the power rail 101 , and the source of the NMOS transistor 108 is connected to the ground rail 102 . The gates of the PMOS transistor 107 and the NMOS transistor 108 are connected to receive signals output from inter...

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PUM

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Abstract

The invention relates to an electrostatic discharge safeguard structure in an integrated circuit, which comprises a first-class electrostatic discharge safeguard component and a second-class electrostatic discharge safeguard component, wherein the first-class electrostatic discharge safeguard component is a diode; the second-class electrostatic discharge safeguard component is a subsection doublestage transistor with a Zener diode; the subsection doublestage transistor with the Zener diode comprises a subsection doublestage transistor, an emitter series resistor, a collector series resistor, a base resistor and the Zener diode; the electrostatic discharge safeguard structure of the integrated circuit provides electrostatic discharge safeguard for an input buffer, an output buffer, a powertrajectory and a ground trajectory; and the electrostatic discharge safeguard component utilizes a subsection doublestage transistor structure in a domain territory and a fictive poly gate structure in each section doublestage transistor to form a series resistor of the Zener diode with low trigger voltage, an emitter and a collector. The invention effectively enhances the electrostatic dischargesafeguard capability of the integrated circuit, reduces the trigger voltage of an electrostatic discharge safeguard circuit, enhances the uniform continuity of the electrostatic discharge safeguard component and effectively saves the domain territory area of the electrostatic discharge safeguard component.

Description

technical field [0001] The invention relates to an electrostatic discharge protection structure, in particular to a structure for improving the electrostatic discharge protection effect through circuit and layout design, and belongs to the technical field of electrostatic protection of integrated circuits. Background technique [0002] Electrostatic discharge is one of the most important reliability issues in CMOS integrated circuits today. With the rapid development of ultra-large-scale integrated circuit technology, the feature size has entered the deep submicron stage, which greatly improves the performance and operation speed of integrated circuits. However, the reduction of device size has greatly increased the sensitivity of the device to external electromagnetic interference, making the harm of electrostatic discharge to the reliability of the device more and more significant. [0003] On the other hand, as the signal transmission speed of integrated circuits increas...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L27/02
Inventor 倪劼陈雷孙华波禹放斌林彦君王文锋王雷张健尚祖宾周雷
Owner BEIJING MXTRONICS CORP
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