A voltage level shifter

Abstract

A voltage level shifter is provided for receiving an input signal from an input voltage domain and converting said signal to a shifted signal in a shifted voltage domain. The voltage level shifter has an input, switching circuitry, a pass transistor and an output. The switching circuitry is configured to isolate an output of said pass transistor from said supply voltage rail when said input voltage domain corresponds to a logical zero.

Description

technical field [0001] The technical field of the invention relates to voltage level shifters for shifting voltage levels between two different voltage domains. Background technique [0002] It is known to provide a voltage level shifter to convert a signal from one voltage domain to a signal suitable for another voltage domain. It allows circuits operating at different voltage levels to interface with each other. [0003] In application-specific integrated circuit (ASIC) design, the circuit design is usually performed by implementing a standard cell (Standard Cell). In this way, ASIC manufacturers can create functional blocks with known electrical characteristics such as propagation delay, capacitance, and inductance that can be expressed in third-party circuit design tools. Standard cell design utilizes these functional blocks to achieve high equivalent gate density (gate density) and good electrical performance. The constraints on circuit components (eg electrical char...

AI Technical Summary

Problems solved by technology

Due to this instability, figure 2 The single NWELL voltage shifter is not available in standard cell libraries for deep submicron technology

Also, in the so-called "FF corner" corresponding to fast NMOS and fast PMOS transistors and high temperature corners where leakage current may be high, even if the logic input is 0, due to the the high resistance path, figure 2 The potential of node 250 may become non-zero

As a result, PMOS transistor 212 may enter a "triode region" (i.e., a linear region) that would weaken the logic of node 252 at the output of circuit 200.

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