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High voltage device

A device and substrate technology, applied in the field of semiconductor devices or integrated circuits, can solve problems such as difficult on-resistance, deterioration of channel well process control, etc.

Active Publication Date: 2014-10-15
GLOBALFOUNDRIES SINGAPORE PTE LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

This results in a short channel length for low drain-to-source on-resistance (Rds on ) becomes difficult
Furthermore, the thin gate electrode used prevents itself from acting as a hard mask, further compromising the process control of forming the channel well

Method used

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Embodiment Construction

[0040] Embodiments of the present invention generally relate to semiconductor devices or integrated circuits. In more detail, some embodiments relate to high power devices. For example, high power devices include lateral double diffused transistors, such as metal oxide transistors (MOS). These high power devices can be used as switching voltage regulators for power management applications. The laterally double-diffused transistors can be easily integrated into devices or integrated circuits. These devices or integrated circuits can be incorporated into or used together with consumer electronics products, and more specifically, can be applied to portable devices such as mobile phones, tablet computers and personal digital assistants (PDAs). consumer products.

[0041] Figure 1 shows a portion 100 of an embodiment of a device. As shown, the portion 100 includes a substrate 101 . The substrate may include a silicon substrate. The substrate may be lightly doped with p-type d...

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Abstract

The invention provides a high voltage device and a method of forming the device.. The method includes providing a substrate prepared with an active device region. The active device region includes gate stack layers of a gate stack including at least a gate electrode layer over a gate dielectric layer. A first mask is provided on the substrate corresponding to the gate. The substrate is patterned to at least remove portions of a top gate stack layer unprotected by the first mask. A second mask is also provided on the substrate with an opening exposing a portion of the first mask and the top gate stack layer. A channel well is formed by implanting ions through the opening and gate stack layers into the substrate.

Description

technical field [0001] The present invention relates generally to semiconductor devices or integrated circuits, and more particularly to high power devices. [0002] Reference to the previous case [0003] This application is a continuation-in-part application claiming the benefit of US Patent Application Serial No. 12 / 390,509 filed February 23,2009. All disclosures are hereby incorporated by reference into this application. Background technique [0004] Lateral Double-Diffused (LD) transistors have been widely used in high voltage applications. For high performance laterally double-diffused transistors, it is desirable to have a low drain-to-source on-resistance (Rds on ) to minimize its power dissipation, and it is desirable to have a high breakdown voltage (breakdown voltage) to maximize its voltage capability (voltage capability). In order to achieve low drain-to-source on-resistance, the channel of the high lateral double-diffused transistor should be as short as po...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/8238H01L21/336H01L27/092H01L29/78H01L29/10
Inventor 张国伟P·R·维尔马
Owner GLOBALFOUNDRIES SINGAPORE PTE LTD