Suppressing fractures in diced integrated circuits

Abstract

The invention relates to suppressing fractures in diced integrated circuits. A semiconductor device has a singulated die having a substrate and a die edge. An interconnect dielectric layer is located on the substrate, and integrated circuit has interconnections located within the interconnect dielectric layer. A trench is located in the interconnect dielectric layer and between a seal ring and a remnant of the interconnect dielectric layer. The seal ring is located within the interconnect dielectric layer and between the trench and the integrated circuit, with the remnant of the interconnect dielectric layer being located between the trench and the edge of the die.

Description

technical field [0001] The present invention relates generally to integrated circuits (ICs) and, more particularly, to singulating IC dies. Background technique [0002] Low-k and ultra-low-k dielectrics and copper metallization are used to improve performance in leading-edge silicon technologies. Although they offer lower dielectric constant and resistivity, respectively, copper interconnects and stacks of these dielectrics can be mechanically fragile. This vulnerability arises from the lower fracture toughness of low-k and ultra-low-k dielectrics relative to silicon dioxide and fluorine-doped silicon dioxide, as well as the lack of adhesion strength between different layers of the dielectric and between the dielectric and copper. reduce. These characteristics can lead to significant yield loss and early failure of ICs utilizing low-k dielectrics. [0003] To ameliorate these problems, it is common practice to add reinforcement structures called seal rings around the edg...

AI Technical Summary

Problems solved by technology

This vulnerability arises from the lower fracture toughness of low-k and ultra-low-k dielectrics relative to silicon dioxide and fluorine-doped silicon dioxide, as well as the lack of adhesion strength between different layers of the dielectric and between the dielectric and copper. reduce

These characteristics can lead to significant yield loss and early failure of ICs utilizing low-k dielectrics

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