Phase locked loop

Abstract

The invention provides a phase locked loop (PLL). The phase locked loop comprises an oscillating clock generator, a phase discriminator, a voltage-controlled oscillator and a frequency dividing module, wherein the oscillating clock generator is used for generating a reference clock signal; the phase discriminator is used for converting difference between the reference clock signal and a clock signal which is output by the frequency dividing module and is subjected to frequency division into a voltage signal; the voltage-controlled oscillator is used for converting the voltage signal into a voltage-controlled oscillator output clock signal; and the frequency dividing module is used for dividing frequency of the voltage-controlled oscillator output clock signal to obtain the clock signal which is subjected to the frequency division according to the frequency error between the reference clock signal and the voltage-controlled oscillator output clock signal and outputting the clock signal which is subjected to the frequency division to the input end of the phase discriminator. The phase locked loop solves the problems of low clock accuracy and high jitter produced by PLL in related technology, and achieves the effect of improving the accuracy of the generated clock signal and reducing the jitter of the generated clock signal.

Description

technical field [0001] The invention relates to the field of image processing and communication, in particular to a phase-locked loop and frequency self-adaptive technology. Background technique [0002] A phase-locked loop (Phase-Locked Loop, PLL) frequency synthesis technique is a commonly used method for accurately determining a frequency at present. There are two technologies that can realize clock synthesis in this technology, namely integer frequency division phase-locked loop technology and fractional frequency division phase-locked loop technology. However, when improving the phase noise performance of the PLL frequency synthesizer, the fractional frequency division PLL technology can provide a narrower step size relative to the reference frequency and a faster FM lock time, in terms of output clock accuracy and smaller jitter There are also greater advantages. In the realization of the concept of fractional frequency division, an all-digital ∑Δ regulator is used t...

AI Technical Summary

Problems solved by technology

[0011] The purpose of the present invention is to provide a phase-locked loop, which can solve the problems of low precision and high jitter of the clock generated by the PLL in the related art

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