Method for downloading field programmable gate array (FPGA) logic codes under joint test action group (JTAG) download mode

Abstract

The invention discloses a method for downloading field programmable gate array (FPGA) logic codes under a joint test action group (JTAG) download mode. In the method, while high-speed parallel downloading of the same FPGA logic codes is supported, different codes are allowed to be configured to the same type of FPGAs and monitoring of the parallel downloading process of each FPGA is simultaneously provided. The method comprises the following steps: inputting the test mode select (TMS) signal, the test clock (TCK) signal, the test data output (TDO) signal and the test data input (TDI) signal, which are simulated by a central processing unit (CPU) port, in the JTAG download signals into a complex programmable logic device (CPLD), educing the independent JTAG download signals to each FPGA from the CPLD and downloading the logic codes into the FPGAs. A system is ensured to have higher autodiagnosis function and redundancy through monitoring and arbitrating each TDO signal.

Description

technical field [0001] The present invention relates to Field Programmable Gate Array (FPGA, Field Programmable Gate Array) configuration technology, in particular to a method for downloading FPGA logic codes in a joint test action group (JTAG, Joint Test Action Group) download mode. Background technique [0002] FPGA is a circuit logic device with both static reprogrammable and online dynamic reconfiguration features. This kind of circuit function is shown as hardware but can be modified by programming like software, thus greatly improving the versatility and design flexibility of the electronic system. The characteristics of FPGA make it widely used in circuit systems, and several or even dozens of FPGAs are often integrated in a circuit board or an array system. [0003] In a multi-FPGA processing system, it is often necessary for the system to use the CPU to complete the download of multi-chip FPGA logic codes. When downloading multiple FPGAs is required, two methods a...

AI Technical Summary

Problems solved by technology

The disadvantage of this method is that the download of each FPGA requires an exclusive data link, and the total download time is the sum of the download time of a single FPGA; and if a certain FPGA in the daisy chain is damaged, it may cause the loading of devices on the entire daisy chain to fail. ; In addition, the consideration of signal quality and signal delay also limits the number of devices that can be mounted in the daisy chain

Another method is to connect the JTAG signals of each FPGA in parallel for downloading, its structure is as follows figure 2 As shown, but this method is suitable for FPGA download of the same logic code, if you want to download logic code for different types of FPGA, you need to occupy other ports of the CPU

Moreover, the CPU can only process one test data output (TDO) signal at the same time, that is to say, if some FPGAs among the multi-chip FPGAs fail to download, the problematic FPGA cannot be found directly through JTAG.

[0004] In the current complex array systems such as backplane systems and laminated board systems, there are more and more examples of multiple FPGA chips, multiple types of FPGAs, and different codes for the same type of FPGA. The above two configuration methods cannot meet the requirements. Debugging requirements for new systems

[0005] For product production and maintenance, such as testing an assembled product or upgrading the code version, disassembling the product or using a download device for debugging are widely criticized by engineers, because they face time risks and confidentiality risk

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