Semiconductor structure and method for forming dual-damascene structure
A dual-damascene structure and patterning technology, which is applied in the fields of semiconductor devices, semiconductor/solid-state device manufacturing, and semiconductor/solid-state device components, etc., can solve problems such as contamination of photoresist and contact hole breakdown.
Inactive Publication Date: 2013-05-29
SEMICON MFG INT (SHANGHAI) CORP +1
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Problems solved by technology
[0012] The problem to be solved by the present invention is to provide a method for forming a dual damascene structure, which solves the problems of contact hole breakdown and nitrogen diffusion contamination of photoresist existing in the existing forming method
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[0030] In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention. However, the present invention can be implemented in many other ways different from those described here, and those skilled in the art can make similar extensions without violating the connotation of the present invention, so the present invention is not limited by the specific implementations disclosed below.
[0031] Secondly, the present invention is described in detail using schematic diagrams. When describing the embodiments of the present invention in detail, for the convenience of explanation, the cross-sectional view showing the device structure will not be partially enlarged according to the general scale, and the schematic diagram is only an example, and it should not be limited here. The protection scope of the present invention. In addition, the three-dimensional space dimensions of length, width and depth should be inc...
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Abstract
The invention provides a semiconductor structure and a method for forming a dual-damascene structure. The method for forming a dual-damascene structure comprises the following steps: providing a semiconductor substrate with a metal wiring layer; forming an etch stop layer, an inter-layer dielectric layer and a protective layer on the metal wiring layer; forming first photoresist patterns on the surface of the protective layer; with the first photoresist patterns as masks, etching the protective layer and part of the inter-layer dielectric layer in turn to form a trench; removing the first photoresist patterns; forming a first bottom anti-reflective coating in the trench; forming a second bottom anti-reflective coating on the surface of the protective layer; forming an isolated layer on the surface of the second bottom anti-reflective coating; forming second photoresist patterns on the surface of the isolated layer; with the second photoresist patterns as masks, keeping etching until the metal wiring layer is exposed to form a contact hole; and removing the second photoresist patterns, the isolated layer, the second bottom anti-reflective coating and the first bottom anti-reflective coating. The invention can prevent the contact hole from being punched through, thereby improving the photoetching precision.
Description
technical field [0001] The invention relates to the field of semiconductor manufacturing, in particular to a method for forming a double damascene structure and a semiconductor structure. Background technique [0002] With the rapid development of semiconductor device manufacturing technology, semiconductor devices already have deep submicron structures. As the number of devices contained in integrated circuits continues to increase, and the size of devices continues to shrink due to the increase in integration, the high-performance, high-density connections between devices are not only performed in a single interconnection layer, but also in multiple layers. interconnection between. Therefore, a multilayer interconnection structure is generally provided in which a plurality of interconnection layers are stacked on each other with an interlayer insulating film interposed therebetween for connecting semiconductor devices. In particular, a multi-layer interconnection structu...
Claims
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IPC IPC(8): H01L21/768H01L23/522
Inventor 王琪
Owner SEMICON MFG INT (SHANGHAI) CORP