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Method for manufacturing semiconductor structure

A manufacturing method and semiconductor technology, applied in the fields of semiconductor/solid-state device manufacturing, semiconductor devices, electric solid-state devices, etc., can solve the problems of packaging failure, low yield, inability to distinguish between diffusion area liner and gate liner, etc. The effect of improving packaging yield

Active Publication Date: 2013-04-03
CSMC TECH FAB2 CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0005] However, there is a problem in the prior art that when the DMOS semiconductor device manufactured by the above method is packaged, since there is no color difference between the gate pad and the diffusion pad, wherein the diffusion pad includes the source pad and Drain pads, so traditional packaging equipment cannot distinguish diffusion pads and gate pads, so it is easy to cause package failure, so the yield of the package is very low

Method used

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  • Method for manufacturing semiconductor structure
  • Method for manufacturing semiconductor structure
  • Method for manufacturing semiconductor structure

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Embodiment Construction

[0030] As can be seen from the background art, in the prior art, since the surface of the semiconductor structure with interconnection plugs is processed into a flat surface before forming the metal pad, the surface of the metal pad formed on the surface of the semiconductor structure is a flat surface, so There is no color difference between the metal pad of the diffusion region and the metal pad of the gate, for example, there is no color difference between the metal pad of the gate and the metal pad of the source, and there is no color difference between the metal pad of the gate and the metal pad of the drain. In this way, it is not easy to distinguish the metal pads in the diffusion region and the metal pads in the gate during packaging, which easily leads to package failure, and thus the packaging yield is very low.

[0031] The inventor of the present invention has conducted a large number of experimental studies and believes that if the above problems are to be overcome...

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Abstract

The invention provides a method for manufacturing a semiconductor structure, which comprises the following steps of: providing a metal oxide semiconductor (MOS) device, wherein a dielectric layer, and first and second contact holes penetrating the dielectric layer are formed in a first diffusion region and a gate region, and the second contact holes is less than the first contact holes; forming ametal layer until the first and second contact holes are completely filled so as to form a first interconnecting plug in the first diffusion region and a second interconnecting plug in the gate region; chemically and mechanically polishing the metal layer; etching the dielectric layer; forming a first diffusion region metal pad on the dielectric layer corresponding to the first diffusion region and the first interconnecting plug, and forming a gate metal pad on the dielectric layer corresponding to the gate region and the second interconnecting plug. The packaging yield of the semiconductor device is improved.

Description

technical field [0001] The invention relates to the technical field of semiconductor manufacturing, in particular to a method for manufacturing a semiconductor structure. Background technique [0002] As the manufacture of integrated circuits develops towards ultra-large scale integrated circuits, the circuit density inside integrated circuits is increasing, and the number of components contained is also increasing. The components need to be connected through metal interconnection lines or metal interconnection plugs. Conductive interconnection. [0003] In the application of semiconductor devices, DMOS transistors are widely used due to their many advantages, including high current driving capability, low on-resistance, and high breakdown voltage. There are two main types of DMOS, vertical double-diffused MOSFET (VDMOSFET for short) and lateral double-diffused MOSFET (LDMOSFET for short). VDMOS is a power device with a vertical double-diffusion structure, which includes a...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/8234H01L21/768H01L21/60
CPCH01L2924/0002
Inventor 陈斌刘海波樊杨刘江
Owner CSMC TECH FAB2 CO LTD