Unit construction of MTP device and operation method thereof

Abstract

The invention discloses a unit construction of MTP device and an operation method thereof. The unit construction comprises a main memory cell, a reference memory cell and a difference comparison circuit. In the method, when the main memory cell is in programmed state, the reference memory cell is in erased state. And when the main memory cell is in erased state, the reference memory cell is in programmed state. Drain currents of the main memory cell and the reference memory cell are compared by the difference comparison circuit. Thus the state of the main memory cell can be still determined after multiple times of programming and erasing, which equivalents to improving the durability of the whole MTP device unit composition.

Description

technical field [0001] The present invention relates to an NVM (Non Volatile Memory, non-volatile memory), in particular to an MTP (Multi-Time Programmable, multi-programmable) NVM device. Background technique [0002] Chinese invention patent application publication CN101373634A (published on February 25, 2009) discloses a MTP device unit structure, which can be manufactured by common CMOS logic process without adding any additional mask or process steps. [0003] see Figure 1a , a conventional MTP cell structure disclosed in the above patent application includes a selection transistor 10 , a programming transistor 20 and an erasing transistor 30 . The source 11 of the selection transistor 10 is used as the drain BL, the gate 12 of the selection transistor 10 is used as the selection terminal SG, and the drain 13 of the selection transistor 10 is connected to the source 21 of the programming transistor 20 . The gate of the program transistor 20 and the gate of the erase t...

AI Technical Summary

Problems solved by technology

[0008] The above-mentioned MTP device cell structure has the following disadvantages: since the erasing uses the FN tunneling mechanism, the erasing efficiency is directly related to the thickness of the gate oxide layer

However, the improvement of the programming voltage needs to increase the isolation distance between the n-well 24 where the programming transistor 20 is located and the n-well 34 where the erasing transistor 30 is located, otherwise it is easy to produce cross-talk between the n-well 24 and the n-well 34, resulting in device failure.

The increase of the isolation distance between the two n-wells 24, 34 increases the cell structure area of ​​the MTP device

The prolongation of the programming time is directly reflected in the deterioration of the performance of the MTP device.

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