Method and device for computing Cyclic Redundancy Check (CRC) code

Abstract

The invention relates to a method and device for computing a Cyclic Redundancy Check (CRC) code. The method comprises the following steps of: computing the cyclic redundancy value of an entire beat datum through a first-stage stream or a multi-stage stream; computing the cyclic redundancy value of a last beat datum in a distributed computing mode of the multi-stage stream; and obtaining the cyclic redundancy value of a data frame according to the cyclic redundancy value of the entire beat datum and the cyclic redundancy value of the last beat datum. By adopting the method and device provided by the invention, the CRC value of a high-frequency data frame can be computed even though the CRC value of the data frame is computed under the condition of large data bit width, and the frequency bottleneck of the computation of the CRC value in high-speed Ethernet application is broken through. A small quantity of resources are occupied, and the method and the device can be popularized to data of any bit width.

Description

technical field [0001] The present invention relates to the field of communication technology, in particular to a method and device for calculating a cyclic redundancy check (Cyclic Redundancy Check, CRC) check code. Background technique [0002] In the data communication system, due to the large data frame, it is often divided into multiple shots and transmitted in parallel. Except for the last beat, other beats transmit the maximum data width. The effective data width of the last beat varies from 1 byte to the maximum byte. If the data frame has only one beat, it is equivalent to the last beat of the multi-beat data. Since the data length of the last shot of the data frame is not fixed, there are many possibilities in the CRC calculation of the last shot of the data frame during the process of calculating the CRC code of the data frame, and the calculation of the CRC check code often becomes a high-speed Ethernet circuit design. frequency bottleneck. The transmission o...

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Problems solved by technology

Considering that the CRC calculation of the last beat data is completed within one clock cycle, in the prior art, 32 CRC calculation modules need to be implemented, which consumes more resources, and due to the large load of the input signal, this method cannot achieve a higher Frequency of

[0008] The large data width and the difficulty in processing the CRC value of the last beat data make the calculation of the CRC operation module often become the frequency bottleneck in the design of high-speed Ethernet circuits

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