Unlock instant, AI-driven research and patent intelligence for your innovation.

Method for manufacturing stackable packaging structure

A technology of packaging structure and manufacturing method, which is applied in semiconductor/solid-state device manufacturing, electrical components, electric solid-state devices, etc., and can solve the problems of increasing manufacturing costs, complex process of intermediary substrate 10, and increasing product thickness, etc.

Active Publication Date: 2011-08-10
ADVANCED SEMICON ENG INC
View PDF0 Cites 9 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

The known stacked packaging structure 1 utilizes the intermediary substrate 10 to electrically connect the chip 20 to the outside. However, the use of the intermediary substrate 10 will increase the thickness of the product, and the process of the intermediary substrate 10 is complicated, which will increase the manufacturing cost.

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Method for manufacturing stackable packaging structure
  • Method for manufacturing stackable packaging structure
  • Method for manufacturing stackable packaging structure

Examples

Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0014] refer to figure 2 , shows a flow chart of the first embodiment of the manufacturing method of the stackable packaging structure of the present invention. with reference image 3 , firstly, referring to step S21 , a first carrier 31 is provided, and the first carrier 31 has a surface 311 . Referring again to step S22 , disposing at least one chip 32 on the surface 311 of the first carrier 31 , the chip 32 includes a first surface 321 , a second surface 322 , an active circuit layer 323 and at least one conductive hole 326 . The active circuit layer 323 is located in the chip 32 and exposed on the second surface 322 , and the conductive hole 326 is located in the chip 32 and connected to the active circuit layer 323 .

[0015] In this embodiment, the chip 32 is a known-good die, and an adhesive 33 is used to adhere the second surface 322 of the chip 32 to the surface 311 of the first carrier 31 . In addition, the chip 32 further includes at least one hole 325, the con...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

No PUM Login to View More

Abstract

The invention relates to a method for manufacturing a stackable packaging structure. The method comprises the following steps of: (a) providing a first carrier; (b) arranging at least one chip on the first carrier; (c) forming a sealing colloid to coat the chip; (d) removing the first carrier; (e) forming a first rerouting layer and at least one first bump; (f) providing a second carrier; (g) arranging one surface of the first rerouting layer on the second carrier; (h) removing partial chip and partial sealing colloid; (i) forming a second rerouting layer; and (j) removing the second carrier.Thus, the second rerouting layer can cause the stackable packaging structure to be more elastic.

Description

technical field [0001] The present invention relates to a method for manufacturing a stackable packaging structure, in particular, relates to a method for manufacturing a stackable packaging structure with redistribution layers and through holes. Background technique [0002] refer to figure 1 , showing a schematic diagram of a known stacked package structure. The known stacked package structure 1 includes an interposer substrate 10 and a chip 20 . The interposer substrate 10 includes a body 11 , several through holes 12 , several conductive traces 13 , several solder pads 14 and several solder balls 15 . The body 11 has a first surface 111 and a second surface 112 . The through holes 12 pass through the body 11 and are exposed on the first surface 111 and the second surface 112 . The conductive traces 13 are located on the first surface 111 of the body 11 and are electrically connected to the through holes 12 . The pads 14 are located on the second surface 112 of the b...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
IPC IPC(8): H01L21/50H01L21/60H01L23/485H01L23/488H01L25/00
CPCH01L2924/15311H01L24/19H01L2224/16225H01L21/568H01L2224/04105H01L2224/12105H01L2224/16227H01L2224/19H01L2924/181H01L2924/00H01L2924/00012
Inventor 余国宠王盟仁
Owner ADVANCED SEMICON ENG INC
Features
  • R&D
  • Intellectual Property
  • Life Sciences
  • Materials
  • Tech Scout
Why Patsnap Eureka
  • Unparalleled Data Quality
  • Higher Quality Content
  • 60% Fewer Hallucinations
Social media
Patsnap Eureka Blog
Learn More

Browse by: Latest US Patents, China's latest patents, Technical Efficacy Thesaurus, Application Domain, Technology Topic, Popular Technical Reports.

© 2025 PatSnap. All rights reserved.Legal|Privacy policy|Modern Slavery Act Transparency Statement|Sitemap|About US| Contact US: help@patsnap.com