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Methods for double-patterning-compliant standard cell design

A double-patterning and cell library technology, applied in computing, electrical components, special data processing applications, etc., can solve problems and other problems

Active Publication Date: 2011-08-10
TAIWAN SEMICON MFG CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, if the first unit and the second unit are adjacent, there will be problems

Method used

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  • Methods for double-patterning-compliant standard cell design
  • Methods for double-patterning-compliant standard cell design
  • Methods for double-patterning-compliant standard cell design

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Embodiment Construction

[0044] The manufacture and use of the embodiments of the present invention are described in detail below. It should be appreciated, however, that the embodiments provide many applicable inventive concepts that may be employed in a wide variety of specific contexts. The specific embodiments described are merely specific ways to make and use the invention, and do not limit the scope of the invention.

[0045] A novel dual patterning design method is provided. Modifications of this embodiment are described below. Like reference numerals are used to designate like elements throughout the various views and illustrative embodiments. Also, the features described below may be in the same photolithographic mask, or alternatively, may be grouped into two photolithographic masks of the same double patterning mask set.

[0046] In the cell library, there are multiple pre-designed standard cells. When laying out an integrated circuit, the standard cells in the cell library are copied t...

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Abstract

A semiconductor chip includes a row of cells, with each of the cells including a VDD line and a VSS line. All VDD lines of the cells are connected as a single VDD line, and all VSS lines of the cells are connected as a single VSS line. No double-patterning full trace having an even number of G0 paths exists in the row of cells, or no double-patterning full trace having an odd number of G0 paths exists in the row of cells. Additionally, the invention also discloses a method of submitting the standard unit design of the double-patterning.

Description

technical field [0001] The present disclosure relates to integrated circuit design, and more particularly, to the use of double patterning techniques to form integrated circuits. Background technique [0002] Double patterning is a technique developed in lithography to increase feature density. Typically, the components of an integrated circuit are formed on a wafer using photolithographic techniques, which include applying a photoresist and defining a pattern in the photoresist. The pattern in the patterned photoresist is first defined in the photomask, and it is realized by transparent or opaque parts in the photomask. Next, the pattern in the patterned photoresist is transferred to the fabricated part. [0003] As the scale of integrated circuits continues to shrink, optical proximity effects are an increasingly large problem. When two separate components come too close to each other, optical proximity effects can cause short circuits between components. To solve this...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L23/50G06F17/50
CPCH01L2924/0002H01L27/11807H01L23/5286H01L27/0207H01L2924/00G06F30/392
Inventor 陈皇宇侯元德李芳松杨稳儒张广兴郑仪侃田丽钧鲁立忠
Owner TAIWAN SEMICON MFG CO LTD