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Image processing apparatus, image processing method, program and integrated circuit

An image processing device and image technology, applied in image communication, television, electrical components, etc., can solve problems such as image distortion, achieve the effect of suppressing band and capacity, and preventing image quality from deteriorating

Inactive Publication Date: 2011-08-24
PANASONIC CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Long groups of pictures (GOP: Group Of Pictures) with multiple flat domains may produce severe distortion in the image

Method used

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  • Image processing apparatus, image processing method, program and integrated circuit
  • Image processing apparatus, image processing method, program and integrated circuit
  • Image processing apparatus, image processing method, program and integrated circuit

Examples

Experimental program
Comparison scheme
Effect test

Embodiment approach 1

[0116] figure 1 It is a block diagram showing the functional configuration of the image processing device in this embodiment.

[0117] The image processing device 10 in this embodiment is a device that sequentially processes a plurality of input images, and includes a storage unit 11 , a frame memory 12 , a readout unit 13 , and a selection unit 14 .

[0118] The selection unit 14 switches and selects between the first processing mode and the second processing mode for each of at least one input image. For example, the selection unit 14 selects the first or second processing mode based on the characteristics and properties of the input image, information related to the input image, and the like.

[0119] When the selection unit 14 selects the first processing mode, the storage unit 11 reduces the input image by deleting information of a predetermined frequency (for example, high-frequency components) contained in the input image, and stores the reduced input image as a reduc...

Embodiment approach 2

[0129] image 3 It is a block diagram showing the functional configuration of the image decoding device in this embodiment.

[0130] The image decoding device 100 in this embodiment corresponds to the H.264 video coding standard, and includes a syntax analysis entropy decoding unit 101, an inverse quantization unit 102, an inverse frequency transformation unit 103, an intra prediction unit 104, an addition unit 105, and a deblocking filter. part 106 , embedding reduction processing part 107 , frame memory 108 , extraction and expansion processing part 109 , full resolution motion compensation part 110 and video output part 111 .

[0131] The image decoding device 100 in this embodiment is characterized by embedding the processing of the reduction processing unit 107 and the extraction and expansion processing unit 109 .

[0132] The syntax analysis entropy decoding unit 101 acquires a bit stream representing a plurality of coded images, and performs syntax analysis and entrop...

Embodiment approach 3

[0243] In Embodiment 2, high-order transform coefficients are always embedded, but when the reduced decoded image is flat and has few edges, that is, when the high-order transform coefficients are small, the image quality may be better if the high-order transform coefficients are not embedded. . In this embodiment, an image quality improvement method in such a case is shown.

[0244] Although the image decoding device in this embodiment has the same image 3 The illustrated image decoding device 100 has the same configuration, but the partial processing operations of the embedding reduction processing unit 107 and the extraction expansion processing unit 109 are different from those of the second embodiment. That is, the embedding reduction processing unit 107 in this embodiment performs the same Figure 4 The embedded processing (step S108) of the encoded high-order transform coefficient shown is Figure 6 Processing shown differs from processing. Furthermore, the extract...

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Abstract

An image processing apparatus (10) wherein the degradation of image quality can be precluded and wherein the band and capacity required for a frame memory can be minimized. The image processing apparatus (10) comprises: a selecting unit (14) that switches between first and second processing modes to select one of the first and second processing modes; a frame memory (12); a storing unit (11) that, when the first processing mode has been selected, deletes predetermined frequency information included in an input image, thereby downsizing the input image, and then stores, as a downsized image, the downsized input image into the frame memory (12) and that, when the second processing mode has been selected, stores an input image into the frame memory (12) without downsizing the input image; and a reading unit (13) that, when the first processing mode has been selected, reads the downsized image from the frame memory (12) to upsize the read downsized image and that, when the second processing mode has been selected, reads the non-downsized input image from the frame memory (12).

Description

technical field [0001] The present invention relates to an image processing device that sequentially processes a plurality of images, and more particularly relates to an image processing device having a function of storing images in a memory and reading the images stored in the memory. Background technique [0002] An image processing device having a function of storing an image in a frame memory and reading the image stored in the frame memory is provided, for example, in an image decoding device such as a video decoder that decodes a bit stream compressed according to a video coding standard such as H.264. In addition, such an image decoding device is used, for example, in a corresponding high-definition digital television or a video conferencing system. [0003] For high-definition images, images with a size of 1920×1080 pixels, that is, images composed of 2,073,600 pixels, are used. Compared with standard image (SDTV) decoders, high-definition decoders require additiona...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H04N7/32H03M7/30
CPCH04N19/00781H04N19/00303H04N7/26329H04N7/26734H04N19/00309H04N7/50H04N7/26287H04N19/00024H04N7/26111H04N7/465H03M7/42H04N19/00127H04N19/00563H04N19/00266H04N19/00296H04N19/00503H04N19/00757H04N7/26271H04N7/26255H04N7/2625H04N7/26015H04N19/105H04N19/132H04N19/172H04N19/18H04N19/182H04N19/184H04N19/428H04N19/48H04N19/59H04N19/61
Inventor W·L·纽V·瓦哈达尼亚林宗顺M·彼米田中健今仲隆晃
Owner PANASONIC CORP