A composite memory having a bridging device for connecting discrete memory devices to a system

Abstract

A composite memory device including discrete memory devices and a bridge device for controlling the discrete memory devices in response to global memory control signals having a format or protocol that is incompatible with the memory devices. The discrete memory devices can be commercial off-the-shelf memory devices or custom memory devices which respond to native, or local memory control signals. The global and local memory control signals include commands and command signals each having different formats. The composite memory device includes a system in package including the semiconductor dies of the discrete memory devices and the bridge device, or can include a printed circuit board having packaged discrete memory devices and a packaged bridge device mounted thereto.

Description

[0001] Cross References to Related Applications [0002] This application claims U.S. Provisional Patent Application No. 61 / 105061, filed October 14, 2008, U.S. Provisional Patent Application No. 61 / 111013, filed November 4, 2008, and U.S. Patent Application No. 61 / 111013, filed March 11, 2009 Priority benefit of Ser. No. 12 / 401963, the disclosures of these earlier applications are expressly incorporated herein by reference in their entirety. technical field Background technique [0003] Semiconductor memory devices are important components in existing industrial and consumer electronic products. For example, computers, mobile phones, and other portable electronic devices all rely on some form of memory to store data. Although many memory devices are generally available as commodity or discrete memory devices, the need for higher integration and higher output (I / O) bandwidth has resulted in Development of embedded memory in which systems like circuits are integrated. [0...

AI Technical Summary

Problems solved by technology

Furthermore, although flash memory has a higher density per unit area than DRAM or SRAM, its performance is limited because its relatively low I / O bandwidth negatively impacts its read and write throughput

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