Matrix inversion device and method based on residue number system

A technology of remainder system and matrix inversion, applied in the field of signal processing, can solve the problems of increasing the length of the critical path, reducing the operating frequency of the system, and increasing the complexity of the basic arithmetic units - multipliers and adders, etc.

Inactive Publication Date: 2011-09-14
UNIV OF ELECTRONIC SCI & TECH OF CHINA
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Problems solved by technology

[0003] The VLSI implementation of the traditional matrix inversion operation unit is based on the binary weight numerical representation system, which is characterized by maturity and simplicity, but with t

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  • Matrix inversion device and method based on residue number system
  • Matrix inversion device and method based on residue number system
  • Matrix inversion device and method based on residue number system

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Embodiment Construction

[0065] The above content of the invention of the present invention will be further described in detail below in conjunction with specific embodiments.

[0066] However, it should not be construed that the scope of the above-mentioned subject matter of the present invention is limited to the following examples. Without departing from the above-mentioned technical idea of ​​the present invention, various replacements and changes made according to common technical knowledge and customary means in this field shall be included in the scope of the present invention.

[0067] See figure 1 , one A matrix inversion device based on a remainder system, comprising:

[0068] The mapping module maps the integers of the two's complement system TCS to the representation range of the remainder system RNS, so that the positive and negative integer representations of the above integers in the RNS are consistent with the TCS;

[0069] Binary-to-remainder system conversion module B2R, realizin...

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Abstract

The invention discloses a matrix inversion device and a matrix inversion method based on a residue number system. Conventional matrix inversion calculation based on a binary complement numerical representation system is divided into a plurality of parallel independent data channels according to a specific residue number base, so that the system complexity and the key path time delay are reduced. Therefore, a matrix inversion calculation structure based on the residue number system comprises a mapping and demapping module, a residue number system and a binary system conversion module, an n-order following matrix calculation module based on the residue number system, an n-order row and column type calculation unit and a sign detection and value zooming module for the residue number system (RNS) integer. A realizing structure based on the residue number system is designed by taking four-order positive definite Hermite matrix inversion as an example; and finally according to the definition of an inverse matrix, only a row and column type value of an original matrix and a following matrix of the original matrix are output.

Description

technical field [0001] The invention belongs to the field of signal processing, and in particular relates to a method and a realization structure of a matrix inversion (MI) based on a remainder system (RNS) in communication and signal processing. Background technique [0002] Contemporary operations and calculations in many signal processing, image processing and communication require high throughput, and many operations are required to be completed in real time, so there is a high requirement for the implementation speed of the algorithm. In digital signal processing, many signal and image processing algorithms have the characteristics of localized operations, intensive calculations, and most of them are matrix operations. The difficulty of matrix operations lies in matrix inversion. Most traditional matrix inversion algorithms are realized by serial computing of processors, which seriously restricts the improvement of computing speed. [0003] The VLSI implementation of t...

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Application Information

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IPC IPC(8): G06F17/16
Inventor 胡剑浩马上李书洋
Owner UNIV OF ELECTRONIC SCI & TECH OF CHINA
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