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Semiconductor structure and forming method thereof

A technology of semiconductor and porous structure, which is applied in the direction of semiconductor devices, semiconductor/solid-state device manufacturing, electrical components, etc., can solve problems affecting device performance, etc., and achieve the effects of improving device performance, suppressing leakage, and improving interface state problems

Active Publication Date: 2014-01-08
TSINGHUA UNIV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0003] The disadvantage of the existing technology is that since Si is different from Ge, III-V group elements and other materials, there will be dislocations between the two materials, which will cause relatively serious scattering and leakage, thereby affecting device performance

Method used

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  • Semiconductor structure and forming method thereof
  • Semiconductor structure and forming method thereof
  • Semiconductor structure and forming method thereof

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Embodiment 1

[0036] Such as figure 1 Shown is a structural diagram of the semiconductor structure of Embodiment 1 of the present invention. The semiconductor structure includes a first material substrate layer 1100, a porous structure layer 1200 formed on the top of the first material substrate layer 1100, and a third material semiconductor layer 1300 formed on the porous structure layer 1200, wherein the porous structure layer 1200 The porosity is generally above 10%, and the porous structure layer 1200 is the second material. The embodiment of the present invention can significantly improve the interface state between the first material substrate layer 1100 and the third material semiconductor layer 1300 . Wherein, the porous structure layer 1200 can be formed by anodic oxidation, and its thickness is about 10 nm to 1000 nm. Specifically, the surface of the porous structure layer 1200 forms a plane after being annealed, thereby facilitating the growth of the third material semiconducto...

Embodiment 2

[0047] In this embodiment, the porous structure layer can also be combined with selective epitaxy, and some dislocations can be isolated through the isolation block, thereby further improving the performance of the device.

[0048] Such as Figure 4 Shown is a structural diagram of the semiconductor structure of Embodiment 2 of the present invention. The semiconductor structure includes a first material substrate layer 2100, a plurality of isolation blocks 2200 formed on the first material substrate layer 2100 at a predetermined distance, and a growth region 2300 is formed between the plurality of isolation blocks 2200, and a growth region 2300 is formed on the growth area. The porous structure layer 2400 in the region 2300 and the third material semiconductor layer 2500 formed on the porous structure layer 2400 . Wherein, the porosity of the porous structure layer 2400 is generally above 10%, and the porous structure layer 2400 is the second material. In one embodiment of t...

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Abstract

A semiconductor structure is provided, comprising: a Si substrate; a porous structure layer formed on the Si substrate, in which the porous structure layer has a flat surface and comprises a Si1-xGex layer with low Ge content; and a Ge-containing layer formed on the porous structure layer, in which the Ge-containing layer comprises a Ge layer or a Si1-yGey layer with high Ge content and x≦̸y. Further, a method for forming the semiconductor structure is also provided.

Description

technical field [0001] The invention relates to the technical field of semiconductor design and manufacture, in particular to a semiconductor structure and a forming method thereof. Background technique [0002] For a long time, the feature size of Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) has been following the so-called Moore's law (Moore's law), and its working speed is getting faster and faster. However, for Si-based material itself As far as it is concerned, it is already close to the double limit of physics and technology. Therefore, various methods have been proposed in order to continuously improve the performance of MOSFET devices, and thus the development of MOSFET devices has entered a so-called post-Moore (More-Than-Moore) era. High-mobility channel engineering based on heterojunction structures, especially material systems such as Si-Ge and Si-C, is one of the effective technologies. [0003] The disadvantage of the existing technology is that...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L29/06H01L29/165H01L21/02
CPCH01L21/0245H01L29/1054H01L21/02513H01L21/02658H01L21/02532H01L21/02381
Inventor 王敬许军郭磊
Owner TSINGHUA UNIV