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Semiconductor packaging piece and manufacturing method thereof

A manufacturing method and semiconductor technology, which are applied in the fields of semiconductor/solid-state device manufacturing, semiconductor devices, and semiconductor/solid-state device components, etc., can solve the problems of increasing the warpage of the chip and the deformation of the stacked semiconductor structure.

Active Publication Date: 2013-01-23
ADVANCED SEMICON ENG INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

In this way, the warpage of the chip will be increased due to the high temperature of the reflow process, resulting in serious deformation of the stacked semiconductor structure

Method used

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  • Semiconductor packaging piece and manufacturing method thereof
  • Semiconductor packaging piece and manufacturing method thereof
  • Semiconductor packaging piece and manufacturing method thereof

Examples

Experimental program
Comparison scheme
Effect test

no. 1 example

[0045] Please refer to figure 1 , which is a schematic diagram of the semiconductor package according to the first embodiment of the present invention. The semiconductor package 100 has a through hole 124 and includes a chip 102, an encapsulant 104, a first dielectric layer 106, a first patterned conductive layer 136, a through hole conductive layer 152, a second patterned conductive layer 138, a second dielectric layer 110 , a plurality of solder balls 112 and a plurality of first solder balls 114 .

[0046] The sealant 104 has a first sealant surface 126 and a second sealant surface 128 opposite to each other.

[0047] The second patterned conductive layer 138 is formed on the second encapsulation surface 128 , and the first wire bonding balls 114 can be formed on the second patterned conductive layer 138 . The position of the first wire ball 114 can overlap with the through hole 124, such as figure 1 The first wire bonding ball 114 on the left is shown in the center. Al...

no. 2 example

[0089] Please refer to Figure 5 , which is a schematic diagram of a semiconductor device according to a second embodiment of the present invention. The parts in the second embodiment that are the same as those in the first embodiment use the same reference numerals, which will not be repeated here. The difference between the semiconductor component 318 of the second embodiment and the aforementioned semiconductor component 118 is that the semiconductor component 318 further includes a plurality of second wire bonding balls 352 .

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Abstract

The invention discloses a semiconductor packaging piece and a manufacturing method thereof. The semiconductor packaging piece is provided with a through hole and comprises a chip, a sealing compound, a dielectric layer, a first patterned conductive layer, a through-hole conductive layer, a second patterned conductive layer and a welding wire ball, wherein the chip is provided with an active surface, a chip back surface and a chip side face and comprises a connecting pad, wherein the connecting pad is formed on the active surface; the sealing compound is provided with a first sealing compound surface and a corresponding second sealing compound surface, wherein the first sealing compound surface is exposed out of the connecting pad, and the sealing compound coats the chip back surface and the chip side face; the dielectric layer is formed on the first sealing compound surface and is provided with an opening exposing the through hole; the through-hole conductive layer is formed in the through hole; the first patterned conductive layer is formed in the opening; the second patterned conductive layer is formed on the second sealing compound surface and extends to the through-hole conductive layer; and the welding wire ball is formed on the patterned conductive layer which is positioned on the second sealing compound surface.

Description

technical field [0001] The present invention relates to a semiconductor package and its manufacturing method, and more particularly to a semiconductor package with stud bump and its manufacturing method. Background technique [0002] A traditional stacked semiconductor structure is formed by stacking multiple chips. Each chip has several solder balls, and the solder balls are formed on the chip by reflow. Another solder ball is used between the chips to electrically connect the chips stacked on each other by means of reflow soldering. [0003] However, the chips go through a reflow process before being stacked, and another reflow process when they are stacked together, that is, each chip goes through at least two reflow processes. In this way, the warpage of the chip will be increased due to the high temperature of the reflow process, resulting in severe deformation of the stacked semiconductor structure. Contents of the invention [0004] The invention relates to a sem...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L23/485H01L23/488H01L23/522H01L25/00H01L21/50H01L21/607
CPCH01L2224/12105H01L24/19H01L2924/15311H01L2225/1035H01L2224/16225H01L21/568H01L2224/19H01L2924/00012
Inventor 陈家庆丁一权
Owner ADVANCED SEMICON ENG INC