Method for predicting negative bias temperature instability (NBTI) service life of pMOSFET (P-channel Metal Oxide Semiconductor Field Effect Transistor) device

An instability and life prediction technology, applied in the direction of single semiconductor device testing, etc., can solve the problems of not considering the simultaneous application of voltage on the gate and drain, limiting the life of the device, and large devices, so as to save the cost of test equipment and failure time short effect

Active Publication Date: 2013-12-25
PEKING UNIV
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  • Application Information

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Problems solved by technology

[0004] In the bias state of the device in actual work, especially for analog and radio frequency (Radio Frequency) applications, the voltage is not only applied to the gate, but also to the drain. Therefore, only applying voltage stress on the gate cannot Fully reflect the working status of the device
The existing technology does not take into account the simultaneous application of voltage to the gate and drain, which cannot fully reflect the actual working state of the device
Additionally, if Figure 5 As shown, at the same gate voltage, when the drain voltage is the supply voltage, the degradation of the device is greater than that of the existing uniform stress case, thus, limiting the lifetime of the device

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  • Method for predicting negative bias temperature instability (NBTI) service life of pMOSFET (P-channel Metal Oxide Semiconductor Field Effect Transistor) device

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[0024] The specific embodiments of the present invention will be described in further detail below in conjunction with the drawings and embodiments. The following examples are used to illustrate the present invention, but not to limit the scope of the present invention.

[0025] Starting from the bias state of the device in actual work, this patent proposes a method for predicting the life of a pMOSFET device by applying a normal power supply voltage to the drain while accelerating stress through a negative bias on the gate, combined with a short channel device structure. This prediction method is not only biased closer to the real working conditions of the device, but under the same gate stress, the device failure time is shorter than the conventional method, so it can better reflect the NBTI life of the pMOSFET device. This method uses a short channel device structure, such as figure 1 As shown, where L is the shortest channel length, a normal power supply voltage is applied to...

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Abstract

The invention discloses a method for predicting a negative bias temperature instability (NBTI) service life of a pMOSFET (P-channel Metal Oxide Semiconductor Field Effect Transistor) device. The method comprises the following steps of: S1, before applying negative bias stress, measuring initial characteristics of the pMOSFET device to obtain initial parameters of the device; S2, applying a stress condition to a grid of the device, wherein drain voltage is normal working voltage; performing stress aging test to the device within a pre-set time interval; S3, testing the parameters of the device to obtain device parameters related to the aging time until the total stress time is ended; S4, when the drain voltage is the normal working voltage, repeating the steps S2 and S3; testing different stress conditions; referencing to the device parameters retrograded to a critical point; obtaining failure times of the pMOSFET device under the relative stress conditions; and S5, using the failure times of the pMOSFET device under the different stress conditions, predicting the reliability service life of the device when the gate voltage is the normal working voltage. Because the failure time of the device obtained by the method in the invention is shorter than that obtained by the conventional method, the NBTI service life of the pMOSFET device can be well reflected.

Description

Technical field [0001] The present invention relates to the technical field of MOS device reliability, in particular to a method for predicting the negative bias temperature instability life of a pMOSFET device. Background technique [0002] With the rapid development of semiconductor technology and the substantial increase in the integration of microelectronic chips, the level of integrated circuit design and processing has entered the era of nano-MOS, the appearance of surface channel devices, the thinning of device oxide layer thickness and the suppression of gate leakage current and The ultra-thin gate oxide layer with high nitrogen content used by the boron penetration effect causes the electric field of the oxide layer to increase, making Negative Bias Temperature Instability (NBTI) and reliability degradation failures become current limiting devices The main reliability problem of proportional reduction is particularly prominent in pMOSFET devices. The conventional test m...

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G01R31/26
Inventor 何燕冬张钢刚刘晓彦张兴
Owner PEKING UNIV
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