Field programmable gate array loading method and device

Abstract

The invention discloses an FPGA loading method and device. The method includes: a processor transmits a compressed configuration file to a CPLD; and the CPLD restores the compressed configuration file to generate a corresponding configuration clock and a configuration control signal line to complete the FPGA. of loading. The invention adopts the method of file compression to transmit the configuration file of the FPGA, which solves the problem of long startup time of the single board caused by the large configuration file, and further achieves the effect of fast startup of the single board.

Description

technical field [0001] The present invention relates to the field of FPGA (Field Programmable Gate Array, Field Programmable Gate Array), in particular to an FPGA loading method and device. Background technique [0002] In practical applications, FPGAs are often used together with processors (such as DSP (Digital Signal Processor, Digital Signal Processor)). For the flexibility of loading FPGAs and the economy of hardware costs, FPGAs often use Slave SelectMAP (passive loading) to load . The schematic diagram of the system connection of the processor loading the FPGA through the CPLD (Complex Programmable Logic Device) is as follows: figure 1 shown. In this loading mode, an external device increases the configuration clock for the FPGA. The general loading process is as follows: [0003] First, the processor reads the configuration data of the FPGA from the non-volatile memory after power-on reset, or through some interfaces, such as EMAC (Ethernet Media Access Controller...

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Problems solved by technology

[0005] The inventor found that the increase of the configuration file directly leads to a large increase in the loading time of the FPGA, thereby greatly increasing the startup time of the single board

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