Die size semiconductor element package and manufacturing method thereof

Abstract

A chip size semiconductor element package and its manufacturing method. The chip size semiconductor element package includes a bare chip, an insulating substrate with a through hole, a first metal layer, a second metal layer and an insulating layer. The first metal layer is disposed on the first surface of the insulating substrate and the first opening of the through hole. The insulating layer covers the second surface of the insulating substrate and surrounds the second opening of the through hole. The second metal is disposed on the insulating layer and the second opening. The bare chip is arranged in the through hole and includes a first electrode and a second electrode. The first electrode is electrically connected to the first metal layer, and the second electrode is electrically connected to the second metal layer. The invention not only saves material cost, but also simplifies the process to improve the yield rate and the competitiveness of the manufacturing cost.

Description

technical field [0001] The invention relates to a semiconductor element package with a die size and a manufacturing method thereof, in particular to a semiconductor element package with a package body close to a die size and a manufacturing method thereof. Background technique [0002] In semiconductor device packaging, the bare chips are generally packaged in a plastic material or a ceramic material, which is usually called a first-level package. Packaging generally requires a carrier to support and protect the die, increase heat dissipation, and provide a system as the input or output of power and signals of the die. [0003] An important indicator of whether the packaging technology is advanced or not is that the ratio of the chip area to the packaging area is closer to 1, the better. The following are several common chip packaging technologies: (1) The initial packaging of the memory chip is a dual in-line package, that is, DIP (Dual ln-line Package), and the size of th...

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Problems solved by technology

[0005] The above-mentioned known semiconductor device packaging not only needs complicated processes such as die bonding, wire bonding, and molding to complete, but also needs to use a lead frame or a substrate of a circuit board to carry the bare chip, thus causing The packaging cost cannot be effectively reduced, and it is necessary to further improve the packaging technology of the above-mentioned known semiconductor elements

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