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A timing control method for physical multi-partition computer architecture

A timing control and system structure technology, applied in the direction of combining various digital computers, generating/distributing signals, etc., can solve problems such as multiple system failures and affect system reliability, and achieve the effect of ensuring reliability

Active Publication Date: 2011-12-14
烟台浪潮云计算有限公司
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Once there is a problem with any group of clock signals, timing control signals, DC power or reset signals in the hardware platform, multiple systems running on it will all fail, which greatly affects the reliability of the entire system

Method used

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  • A timing control method for physical multi-partition computer architecture
  • A timing control method for physical multi-partition computer architecture
  • A timing control method for physical multi-partition computer architecture

Examples

Experimental program
Comparison scheme
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Embodiment

[0028] Legacy IO controllers use two different timing control methods when the system is divided into multiple independent multiprocessor systems or coupled into a complete computer system:

[0029] Timing Control for Multiprocessor Systems:

[0030] 1. Set the Legacy IO controller of the partition through the system management unit, and activate the Legacy IO controller of each partition;

[0031] 2. Each partition can be turned on and off independently. After a partition receives the power-on command, the Legacy IO controller sends an enable signal to the DC power supply group of the partition. Power supply, and feedback Power good signal to Legacy IO controller;

[0032] 3. The Legacy IO controller sends an enable signal to the partition clock unit, and this clock unit provides clocks to the computing units, storage units, and input and output units in the partition;

[0033] 4. After the Legacy IO controller waits until the system clock is stable, it resets the computing...

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PUM

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Abstract

The invention discloses a novel timing control method of a computer architecture based on NUMA (non-uniform memory access). In a computer with multiple physical layer partitions, each hardware platform is provided with an independent power system and a clock system; and the input / output unit of each partition is provided with a LegacyIO controller, and the power sequence, clock enable and resetting system of the partition are controlled by the LegacyIO controller. Therefore, when certain partition fails, other partitions can work normally as each partition is provided with the independent timing control system, power system, clock system and resetting system, so that the system reliability is fully ensured; and simultaneously, the computer of each partition can be turned on and off independently without influencing the normall work of other partitions, thus online maintenance of the system is possible.

Description

[0001] technical field [0002] The present invention relates to a technical field of computer applications, in particular to a timing control method of a physical multi-partition computer architecture. Background technique [0003] Ordinary NUMA or SMP multiprocessor architectures usually only have a unified set of timing, clock, power, and reset systems. Even if the virtualization technology is used to realize the multi-system architecture, each system also uses a hardware platform, and only has a fixed sequence, clock, power supply, and reset system. Once any set of clock signals, timing control signals, DC power supply or reset signals in the hardware platform has a problem, multiple systems running on it will all fail, greatly affecting the reliability of the entire system. Ordinary NUMA or SMP multiprocessor architecture diagram is as follows figure 1 shown. SUMMARY OF THE INVENTION [0004] The purpose of the present invention is to provide a time sequence contro...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F15/16G06F1/04
Inventor 李博乐林楷智叶丰华王欢
Owner 烟台浪潮云计算有限公司
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