Hierarchical Block Irregular Low Density Check Code Decoder and Decoding Method

A low-density check code and decoder technology, which is applied in the field of layered and block irregular low-density check code decoders and decoding, to achieve the effects of eliminating pipeline conflicts, small resource consumption, and saving hardware resources

Active Publication Date: 2011-12-14
SHANGHAI NAT ENG RES CENT OF DIGITAL TELEVISION
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Problems solved by technology

[0004] Aiming at the deficiencies in the prior art, the present invention proposes a layered block non-regular low-density check code decoder and a decoding method, and the improved decoding The device structure does not require an interleaving network, which saves hardware resource consumption, has very small...

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  • Hierarchical Block Irregular Low Density Check Code Decoder and Decoding Method
  • Hierarchical Block Irregular Low Density Check Code Decoder and Decoding Method

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Embodiment Construction

[0050] The embodiments of the present invention are described in detail below in conjunction with the accompanying drawings: this embodiment is implemented on the premise of the technical solution of the present invention, and detailed implementation methods and specific operating procedures are provided, but the protection scope of the present invention is not limited to the following the described embodiment.

[0051] Such as figure 1 Shown is the mother matrix of the quasi-cyclic LDPC code and its extension method used by a decoder with a degree of parallelism k. The size of the codeword to be constructed is m*n, and the size of the corresponding mother matrix is ​​(m / k)*(n / k), and each element in the mother matrix is ​​expanded into a k*k matrix. The 0 in the mother matrix is ​​expanded into a k*k zero matrix; the 1 in the mother matrix is ​​expanded into a cyclic shift form of a k*k unit matrix. In the figure, the left side is the mother matrix diagram, and the ...

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Abstract

The invention discloses a laminated and partitioned irregular low density parity check (LDPC) code decoder and a decoding method in the technical field of communication. An external information storage unit outputs a soft value transmitted to an information node by a last iterated check node to a decoding processing module. A cyclic shift register transmits a posterior probability likelihood ratio update value of the information node to the decoding processing module. The decoding processing module transmits the check update value in the iteration to the external information storage unit, andsimultaneously transmits the posterior probability likelihood ratio update value of the information node to the cyclic shift register through a decoding processing module interweaving network. The decoder is suitable for decoding all quality control (QC) LDPC codes, and all the partitioned LDPC code words support decoding; the decoder has no stream competition conflict, and has better throughput performance and relatively simple working time sequence; and the consumption of the interweaving network of huge resources is not needed, many hardware resources are saved, and the resource consumption of the whole decoder is relatively low. The decoding supporting parallelism degree can be flexibly changed.

Description

technical field [0001] The invention relates to a decoder and a decoding method in the field of communication technology, in particular to a layered block irregular low-density check code decoder and a decoding method. Background technique [0002] Low Density Parity Check Codes (LDPC Codes) is a coding technology first proposed by Gallager in 1963. It has performance close to the Shannon limit. It has become a research hotspot in the field of coding and is widely used in various Standards in the field of wireless communication include my country's digital TV terrestrial transmission standard, the European second-generation satellite digital video broadcasting standard, IEEE 802.11n, IEEE 802.16e, etc. In the current wireless communication, people pay more and more attention to the communication of high data rate, so the LDPC decoder with simple structure and high throughput has always been the research focus of LDPC codes. In addition, in practical applications, codes with ...

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Application Information

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IPC IPC(8): H04L1/00
Inventor 杨艺宾王轶翔崔靖俞晖徐友云
Owner SHANGHAI NAT ENG RES CENT OF DIGITAL TELEVISION
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