A kind of semiconductor device and its manufacturing method

Abstract

The invention has the following beneficial effects: in the process of preparing CMOS (complementary metal-oxide-semiconductor) transistors by adopting the replacement gate or gate last, after high-k gate dielectric layers are formed in the NMOS device region and the PMOS device region, a first work function adjustment dielectric layer belonging to the NMOS region and a second work function adjustment dielectric layer belonging to the PMOS region are respectively formed to adjust the threshold voltages of the NMOS device and the PMOS device respectively, and formed by dielectric materials, the work function adjustment dielectric layers are easier to selectively etch and beneficial to process control and also relieve the pressure on research on dual metal gate materials.

Description

technical field [0001] The present invention generally relates to a semiconductor device and a manufacturing method thereof, in particular to a high-k gate dielectric / metal gate device based on a gate replacement process and a manufacturing method thereof. Background technique [0002] With the development of semiconductor technology, integrated circuits with higher performance and stronger functions require greater component density, and the size, size and space of each component, between components or each component itself also need to be further reduced. The application of 22nm and below process integrated circuit core technology has become an inevitable trend in the development of integrated circuits, and it is also one of the topics that major international semiconductor companies and research organizations are competing to research and develop. CMOS device gate engineering research centered on "high-k gate dielectric / metal gate" technology is the most representative co...

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Problems solved by technology

[0003] In the traditional gate replacement process, the typical process includes forming a dummy gate of polysilicon or silicon nitride, and after the source / drain is formed, the dummy gate is etched away to form a gate trench, and then sequentially in the gate trench Deposit high-k gate dielectric and dual-metal gate electrode materials. For dual-metal gate electrode materials, metals with different work functions need to be formed in the gate trench regions of nMOS and pMOS devices to adjust the threshold voltage of the device. However, due to the metal etching process The complexity on the surface brings difficulty to the integration of CMOS integrated process

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