High speed, low power consumption, isolated analog CMOS unit

Abstract

A semiconductor device 100 has N-well regions 18 holding PMOS devices 110, 112 and P-type regions 14 holding NMOS devices 114, 116. Devices 110 and 114 have high thresholds and devices 112 and 116 have low thresholds. The PMOS devices are junction isolated from the substrate 10 by the N-well 18 and the NMOS devices are isolated from the substrate by the N-type layer 13. Field oxide regions 20 laterally isolate the PMOS from the NMOS devices. The high threshold CMOS devices 110, 114 connect the low threshold CMOS devices to opposite rails Vdd and Vss. A control terminal 121 turns the high threshold devices on to let the low threshold devices switch rapidly. In stand-by mode, the high threshold devices are off and there is very low leakage current.

Description

[0001] Cross reference to related applications [0002] This application claims the benefit of the priority date of US Patent Application No. 12 / 365,228 filed on February 4, 2009, and the specification of the patent application is hereby incorporated by reference. Background technique [0003] MOSFET technology can be used to make high-speed and low-power consumption circuits for mobile, computing, communications and consumer products. However, the requirements for handling high speed and low power consumption usually require a basic compromise. In mobile applications such as cellular phones, high speed and low power consumption are key criteria. Generally, optimizing one criterion will negatively affect another criterion. A low threshold voltage (the voltage between the source and gate of the MOSFET, when it appears, the current first starts to flow in the transistor) is always preferred for high-speed MOSFETs. The relatively high threshold voltage reduces the MOSFET off-state ...

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Problems solved by technology

However, high-threshold voltage devices switch more slowly than low-threshold

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