A method for dynamically reconfigurable processing cell array expansion
A processing unit and array technology, applied in the field of dynamic reconfigurable processing unit array expansion, can solve the problems of the small number of dynamically reconfigurable processor units and the inability to meet the needs of the amount of calculation, and achieve the advantages of performance, calculation width and The effect of increasing depth
Active Publication Date: 2016-03-16
TSINGHUA UNIV
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Problems solved by technology
[0005] In the existing technology, the number of dynamically reconfigurable processor units is relatively small, which cannot meet the demand for increasingly large amount of calculation
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[0029] In order to make the above objects, features and advantages of the present application more obvious and comprehensible, the present application will be further described in detail below in conjunction with the accompanying drawings and specific implementation methods.
[0030] In order to facilitate the description of this application, firstly, a schematic diagram of the structure of a typical dynamic reconfigurable processor is introduced as figure 1 shown. combine figure 1 , the operation process of the dynamically reconfigurable processor can be summarized as the following steps:
[0031] 1. The external data read-in device 42 of the dynamically reconfigurable processor reads the data to be processed in the memory outside the processor into the processor, and distributes it to the external data buffers 31 in the processing of multiple sub-units.
[0032] 2. Multiple subunits read 31 data from their respective external data buffers, and then process them. Multiple ...
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The invention provides a method for dynamic reconfigurable processing element array expansion, relating to the technical field of a dynamic reconfigurable processor of an embedded system. The method comprises the following steps: determining the number of lines m and the number of rows n after the processing element array expansion according to the number of lines a and the number of rows b of a basic processing element array, wherein a is smaller than m, and b is smaller than n; expanding a basic a * b processing element array into an m * n processing element array; and correspondingly adjusting configuration information of a route unit, an internal data reading device, an internal data writing device, a time sequence control unit and a processing unit array according to the m * n processing element array after expansion. By adopting the application, the basic processor unit array can be expanded into a wider and deeper processor unit array, the calculation width and depth of a dynamic reconfigurable processor can be increased, performance optimization can be facilitated, and requirements of the processing of more data can be satisfied.
Description
technical field [0001] The present application relates to the technical field of dynamically reconfigurable processors in the field of embedded systems, in particular to a method for expanding a dynamically reconfigurable processing unit array. Background technique [0002] Dynamic reconfigurable processor is a new processor architecture, which has significant advantages over previous single-core processors, dedicated chips, and field programmable logic arrays, and is a direction for the development of future circuit structures. [0003] First of all, a dynamically reconfigurable processor often contains multiple arithmetic logic units, and the number is huge, which is called a many-core array. The array is equipped with a highly flexible routing unit to realize the diversified interconnection between the arithmetic and logic units. Therefore, the many-core array connected by the routing unit can realize high-speed processing of data streams, and has a huge advantage in per...
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IPC IPC(8): G06F15/78
Inventor 刘雷波王延升朱敏邹于佳杨军曹鹏时龙兴尹首一魏少军
Owner TSINGHUA UNIV