Ashing treatment method for semiconductor process

Abstract

The invention relates to an ashing treatment method for a semiconductor process. The ashing treatment method comprises the following steps of: (a) providing an etched front-end device layer structure provided with a polymer to be removed; and (b) carrying out first ashing treatment on the etched front-end device layer structure so as to remove the polymer, wherein the first ashing treatment is direct current ashing treatment. According to the ashing treatment method for the semiconductor process, the transverse action in the ashing process can be reduced, thereby ensuring that the influence on the shape of the side wall of an etching structure can be reduced as much as possible while the polymers attached to the bottom and the side wall of the etching structure are removed, the etching structure with a better side wall shape is effectively ensured and further the finished product rate and the reliability of the device are ensured; in addition, the method disclosed by the invention is improved on the basis of a traditional ashing treatment method, not only retains the advantages of a traditional process and can be used for effectively removing photoresist and the polymer attached to the surface of the etching structure.

Description

Technical field [0001] The present invention relates to a semiconductor manufacturing process, and more particularly, the present invention relates to an ashing treatment method used in a semiconductor process. Background technique [0002] As one of the important processes of semiconductor technology, the photolithography process usually includes the following steps: spin-coating photoresist on the semiconductor wafer to form a photoresist layer; selectively expose the photoresist layer, and make the exposure through a development step The latter photoresist layer is further formed with a photoresist pattern; the semiconductor wafer is etched using the photoresist layer as a mask; and an ashing treatment step after the etching is completed. [0003] As the feature size of VLSI devices continues to shrink in proportion and the degree of integration continues to increase, the requirements for etching technology that can completely copy the mask pattern to the surface of the substrat...

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Problems solved by technology

[0007] However, since a certain amount of F ions remain in the polymer, when it is processed by a conventional plasma ashing treatment method, since the conventional plasma method is isotropic, the removal of the etched structure bottom At the same time as the polymer, the plasma gas will remove the sidewall polymer at the same rate as the removal rate of the bottom polymer, so that the F ions can quickly combine with the plasma gas to destroy the sidewall shape of the etched structure, especially when the formation occurs Offset etched structures (i.e., such as figure 1 The destruction of the shape of the sidewall will be more serious when etching the structure 106b) as shown, and even lead to further damage to the sidewall, thereby reducing the process window, resulting in a decrease in the stability of the formed semiconductor device, and ultimately affecting the electrical performance

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