Method for extracting length of effective grid electrode
A technology of gate length and gate width, which is applied in the direction of measuring devices, instruments, and electrical devices, to achieve the effects of improving test speed, reducing device waste, and reducing costs
Active Publication Date: 2013-06-12
SHANGHAI HUAHONG GRACE SEMICON MFG CORP
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Problems solved by technology
[0005] The technical problem to be solved by the present invention is a method for extracting the effective gate length, which obtains the effective gate length by indirectly testing the capacitance, thereby reducing device waste, reducing test cost, and improving test speed
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[0022] In order to make the objectives, technical solutions and advantages of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings.
[0023] Such as figure 1 In the N-type MOS transistor shown, if a positive voltage exceeding the threshold voltage of the MOS transistor is applied to the gate 11, and the source 12, the drain 13, and the substrate 14 are all grounded, the MOS transistor is close to the channel position of the gate oxide layer 15. Enter the inversion state. At this time, the MOS transistor is equivalent to the plate capacitance. The total capacitance of the MOS transistor is equal to the sum of the gate-source capacitance 16, the gate substrate capacitance 17, and the gate-drain capacitance 18, which is C total =C gso +C gg +C gdo . Since it can be equivalent to a plate capacitor at this time, C total =C u ×L×W, where C total Is the total capacitance of the MOS transistor,...
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The invention provides a method for extracting the length of an effective grid of a metal oxide semiconductor (MOS) transistor, which comprises the steps of: providing a reference MOS transistor, wherein the parameters of the reference MOS transistor respectively comprise total capacitance Cta, unit capacitance Cua, the length La of a layout design parameter grid, the number Na of the grid and the width Wa of the grid; and providing an MOS transistor to be tested, wherein the parameters of the MOS transistor to be tested respectively comprise the length Lb of the effective grid, total capacitance Ctb of the total MOS transistor, unit capacitance Cub, the number Nb of the layout design parameter grid, and the width Wb of the grid. The length Lb of the effective grid can be obtained by testing the total capacitance of the reference MOS transistor and the MOS transistor to be tested. The test of the capacitance is greatly simpler than the test by a physical method directly using a sample, so that the method of the embodiment is beneficial to reducing the waste of devices, reducing the test cost, and accelerating the test speed of the length of the effective grid.
Description
Technical field [0001] The invention relates to a method for semiconductor testing, in particular to a method for extracting an effective gate length. Background technique [0002] In the field of integrated circuits, the feature size represents the smallest size that a device can achieve. The feature size not only affects the integration of the circuit, but also has a great impact on the performance of the device. Therefore, the feature size must be determined before the device is used. [0003] For MOS transistors, the effective gate length is an important feature size in the process. Before the MOS transistor integrated circuit is taped out, the corresponding layout of the device is first designed. The most important part includes designing the gate length (Poly CD or Drawn PolyCD) of the MOS transistor. Due to the various process errors in the actual microelectronics manufacturing process, there will be a certain error between the originally designed gate length (Poly CD) and ...
Claims
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IPC IPC(8): H01L21/66G01B7/02
Inventor 韦敏侠张瑛
Owner SHANGHAI HUAHONG GRACE SEMICON MFG CORP