Multi-chip packages and manufacturing method thereof

Abstract

The invention discloses multi-chip packages and manufacturing method thereof. The multi-chip package may include a package substrate, a plurality of semiconductor chips and conductive connecting members. The semiconductor chips may be sequentially stacked on the package substrate. Each of the semiconductor chips may include a signal pad and a test pad. The conductive wires may be electrically connected between the signal pad of an upper semiconductor chip among the semiconductor chips and the package substrate via the test pad of a lower semiconductor chip under the upper semiconductor chip. The test pad may be converted into the dummy pad by cutting a fuse.

Description

[0001] This application claims priority from Korean Patent Application No. 10-2010-0086791 filed with the Korean Intellectual Property Office (KIPO) on Sep. 6, 2010, the entire contents of which are hereby incorporated by reference. technical field [0002] Example embodiments relate to multi-chip packages and methods of manufacturing the same. More particularly, example embodiments relate to a multi-chip package including a plurality of semiconductor chips stacked sequentially and a method of manufacturing the same. Background technique [0003] Generally, a plurality of semiconductor fabrication processes may be performed on a semiconductor substrate to form a plurality of semiconductor chips. In order to mount the semiconductor chip on a printed circuit board (PCB), a packaging process may be performed on the semiconductor chip to form a semiconductor package. [0004] In order to increase the storage capacity of a semiconductor package, a multi-chip package including a ...

AI Technical Summary

Problems solved by technology

This results in an increase in the size of the semiconductor chip, so that the multi-chip package will have a large

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