Single event upset-resisting scanning structure D trigger capable of setting and resetting

An anti-single-event, trigger technology, applied in the direction of electrical pulse generator circuits, pulse generation, electrical components, etc., can solve the problem of low anti-single-event flipping ability.

Active Publication Date: 2012-03-28
NAT UNIV OF DEFENSE TECH
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0009] The technical problem to be solved by the present invention is to propose a settable and resettable anti-single event flip-flop scanning structure D flip-flop that ha

Method used

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  • Single event upset-resisting scanning structure D trigger capable of setting and resetting
  • Single event upset-resisting scanning structure D trigger capable of setting and resetting
  • Single event upset-resisting scanning structure D trigger capable of setting and resetting

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Embodiment Construction

[0034] figure 1 It is a schematic diagram of the logical structure of a scanning structure D flip-flop that can be set and reset against single event reversal in the present invention. The present invention consists of a clock circuit (such as figure 2 shown), scan control buffer circuit (such as image 3 shown), reset buffer circuit (such as Figure 4 shown), the master latch (as Figure 5 shown), slave latches (such as Figure 6 shown) and the output buffer circuit (as Figure 7 shown) composition. The present invention has six inputs and one output. The two input terminals are CK is the clock signal input terminal, D is the data signal input terminal, SE is the scan control signal input terminal, SI is the scan data input terminal, SN is the set signal input terminal and RN reset signal input terminal; one The output terminal is Q, that is, the data output signal terminal. The clock circuit receives CK, and outputs C and CN respectively after buffering CK. The sca...

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Abstract

The invention discloses a single event upset-resisting scanning structure D trigger capable of setting and resetting, which aims at improving the single event upset-resisting capability of the single event upset-resisting scanning structure D trigger. The trigger comprises a clock circuit, a scanning control buffer circuit, a resetting buffer circuit, a main latch, a slave latch and an output buffer circuit, wherein the main latch comprises twenty PMOS (P-channel metal oxide semiconductor) tubes and twenty NMOS (N-channel metal oxide semiconductor) tubes, the slave latch comprises ten PMOS tubes and ten NMOS tubes, double-die redundant strengthening is carried out on the main latch and the slave latch respectively, and a C2MOS circuit structure in the main latch is improved, namely upper pulling circuits and lower pulling circuits in the C2MOS circuits which are mutually redundant. The single event upset-resisting scanning structure D trigger has strong single event upset-resisting capability, suitable for a standard unit library of a single event upset-resisting strengthening integrated circuit, and applied to the fields of aviation, spaceflight and the like.

Description

technical field [0001] The invention relates to a master-slave D flip-flop with a settable and resettable structure and a scanning structure, in particular to a single-event upset (signal event upset) capable settable and resettable scanning structure D flip-flop. Background technique [0002] In cosmic space, there are a large number of high-energy particles (protons, electrons, heavy ions) and charged particles. After the integrated circuit is bombarded by these high-energy particles and charged particles, an electronic pulse will be generated in the integrated circuit, which may cause the original level of the internal node of the integrated circuit to flip. This effect is called single event upset (SEU). The higher the LET (Linear Energy Transfer) value of a single event bombarding an IC, the stronger the resulting electron pulse. Integrated circuits used in aviation and aerospace fields are threatened by single event upsets, which can make integrated circuits work unst...

Claims

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Application Information

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IPC IPC(8): H03K3/013H03K3/02
Inventor 刘必慰池雅庆梁斌李鹏刘祥远孙永节胡春媚陈建军何益百杜延康秦军瑞
Owner NAT UNIV OF DEFENSE TECH
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