Method and device for synchronizing clocks

A clock synchronization and master clock technology, applied in the field of communication, can solve problems such as low synchronization accuracy, uncertain bidirectional path, asymmetry, etc., to achieve the effect of eliminating uncertainty and asymmetry, and solving low synchronization accuracy

Inactive Publication Date: 2012-03-28
山东海润数聚科技有限公司
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0008] The main purpose of the present invention is to provide a clock synchronization method and device to at least solve the low synchronization accuracy caused by the uncertainty of the network link delay and the asymmetry of the two-way path introduced by the physical layer chip in the prior art The problem

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  • Method and device for synchronizing clocks
  • Method and device for synchronizing clocks
  • Method and device for synchronizing clocks

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Embodiment 1

[0027] figure 1 It is a preferred structural diagram of a clock synchronization device according to an embodiment of the present invention, which includes: a processor 202, a clock unit 204, and a physical layer chip 206. Preferably, the clock synchronization device in this embodiment may also include: a switch Chip 208 .

[0028] The functions and interrelationships of each module in the above clock synchronization device will be described respectively below.

[0029] 1) Physical layer chip (PHY) 206: In addition to completing the physical layer codec function, it also realizes functions such as IEEE 1588 message detection and time stamp generation. Time synchronization with the main clock is realized by receiving the second pulse signal and the TOD signal output by the clock unit.

[0030] The present invention provides a preferred physical layer chip, such as figure 2As shown, the physical layer chip (PHY): includes a codec module, a 1588 message detector and a time sta...

Embodiment 2

[0052] exist Figure 1-Figure 2 On the basis of the clock synchronization device shown, the present invention also provides a clock synchronization method, such as Figure 4 As shown, it includes: .

[0053] S402, calculating frequency drift and time offset between the local clock and the master clock;

[0054] S404, use the frequency drift to calibrate the local clock, and use the time offset to calibrate the second pulse signal;

[0055] S406, using the calibrated local clock, the calibrated second pulse signal, and the time value TOD of the rising edge of the calibrated second pulse signal to set the working clock and time stamp module in the physical layer chip Time is synchronized.

[0056] In the technical solution provided by this embodiment, use the calibrated local clock and the calibrated second pulse signal and TOD to synchronize the working clocks in multiple physical layer chips, so that the frequency of the working clock CLK of the physical layer chip is the s...

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Abstract

The invention discloses a method and a device for synchronizing clocks. The method comprises the following steps of: calculating frequency drift and time migration between a local clock and a master clock; calibrating the local clock by using the frequency drift, and calibrating second pulse signals by using the time migration; and synchronizing the time of work clocks and time stamp modules in physical layer chips by using TOD (time of date) of the calibrated local clock, the calibrated second pulse signals and the rising edge of the calibrated second pulse signals. According to the method and the device, the problem of low synchronization accuracy caused by nondeterminacy of network link delay introduced by the physical layer chips and asymmetry of duplex paths in the prior art is solved, and the time of a plurality of physical layer chips and the master clock is synchronized.

Description

technical field [0001] The present invention relates to the communication field, in particular to a clock synchronization method and device. Background technique [0002] With the all-IP development of networks and services, the packet network will replace the TDM (Time Division Multiplexing) network and become the mainstream bearer network. TDM network is a clock synchronization system (that is, frequency synchronization system), while traditional packet network is an asynchronous system. In order to achieve compatibility with TDM services and interconnection with TDM networks, packet networks need to provide high-quality clock synchronization functions. [0003] In addition, mobile communication puts forward higher requirements for network synchronization. TD-SCDMA, CDMA2000, and LTE all have high-precision time synchronization requirements. It can also be satisfied by GPS, but GPS has problems in safety and engineering installation and maintenance. Therefore, operators ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H04J3/06
Inventor 郭俊俊
Owner 山东海润数聚科技有限公司
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