Prototype verification device for programmable logic devices

Abstract

The invention relates to a prototype verification device for programmable logic devices. The prototype verification device comprises a back plate, at least two card slots connected to the back plate, and sub-cards inserted into the card slots, wherein the at least two sub-cards are connected through the back plate; each sub-card comprises a core plate and an adapter plate which are connected through a first connector; the adapter plate is connected to the back plate; the core plate is provided with a programmable logic device array; and the programmable logic device arrays on the at least two sub-cards are connected through the adapter plates, which are connected to the back plate, of the at least two sub-cards. The prototype verification device for the programmable logic devices has a modular and open extensible framework, the core plates can be in flexible connection with the back plate through the adapter plates according to the requirement, and a testing device is quickly constructed according to different requirements, so that one verification device is suitable for testing various chips, and cost is saved.

Description

technical field [0001] The invention relates to the technical field of IC chip testing, in particular to a programmable logic device prototype verification device. Background technique [0002] As the performance and complexity of current chips continue to increase, various defects that have never appeared before pose new challenges to traditional testing methods. It is imperative to develop a serialized test verification device suitable for chip development. An IC project integrates and classifies the requirements of the verification device, and the same series can be applied in multiple similar projects, thus avoiding the resource waste and schedule delay caused by the separate development of the verification device for each project; the test verification device can be expanded It has strong versatility and versatility, can be quickly built according to different project requirements, and is compatible with multiple projects. It is the development trend of prototype verifi...

AI Technical Summary

Problems solved by technology

[0003] The FPGA test method and device provided by the prior art has a fixed structure and is not easy to expand. A test device is limited to a very specific application and corresponds to a specific function test

Develop a proprietary verification setup for each chip, greatly increasing the cost of testing

In addition, the FPGA prototype verification device provided by the prior art has a low reuse rate, especially for large chip developers, who need to develop dozens of chips at the same time, and the verification device developed for each chip cannot be reused, which causes a waste of resources on the one hand. On the other hand, it is not possible to quickly build prototype verification devices and systems

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