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Forming method of shallow trench isolation structure

A technology of isolation structure and shallow trench, which is applied in the direction of electrical components, semiconductor/solid-state device manufacturing, circuits, etc., can solve problems such as short circuit and punch-through, and achieve the effects of avoiding loss, reducing wet etching time, and avoiding punch-through or short circuit

Active Publication Date: 2014-07-30
SEMICON MFG INT (SHANGHAI) CORP +1
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Problems solved by technology

However, punch-through or short circuits usually occur between the polysilicon gate structures formed on the surface of the substrate 100

Method used

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  • Forming method of shallow trench isolation structure
  • Forming method of shallow trench isolation structure
  • Forming method of shallow trench isolation structure

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Embodiment Construction

[0012] It can be seen from the background art that punch-through or short circuit usually occurs between the polysilicon gate structures formed on the surface of the substrate 100 . For this reason, the inventors of the present invention have found through research that the punch-through or short-circuit phenomenon is due to the fact that the shallow trench isolation structure 101 located between the polysilicon gate structures and higher than the surface of the substrate 100 is too narrow to effectively electrically isolate Adjacent polysilicon gate structures, so that the adjacent polysilicon gate structures have a punch-through or short circuit phenomenon.

[0013] After further research by the inventors, it was found that the reason why the shallow trench isolation structure above the substrate surface was too narrow was that the hard mask layer and the pad oxide layer were removed by a wet method, while the pad oxide layer and the shallow trench The material used for the ...

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Abstract

The invention provides a forming method of a shallow trench isolation structure, and is characterized by comprising providing a substrate, wherein a liner oxide layer and a hard mask layer are sequentially formed on the surface of the substrate; forming a trench on the hard mask layer, on the liner oxide layer and in the substrate; forming a filling dialectic layer which fills the trench; removing the hard mask layer and exposing the liner oxide layer; carrying out doped ion implantation on the exposed liner oxide layer, so as to form a doped liner oxide layer; and removing the doped liner oxide layer to expose the substrate. The invention can prevent punch-through or short circuit from happening to adjacent polysilicon gate structures which are formed at both sides of the shallow trench isolation structure.

Description

technical field [0001] The invention relates to the field of semiconductor manufacturing, in particular to a method for forming a shallow trench isolation structure. Background technique [0002] As semiconductor technology enters the deep sub-micron era, components below 0.18 microns, such as CMOS integrated circuits, mostly use shallow trench isolation structures for lateral isolation between active regions, and more can be found in US Patent No. US7112513 Information about Shallow Trench Isolation Technology. [0003] The shallow trench isolation structure is a device isolation technology, and its specific process includes: providing a substrate with a pad oxide layer and a hard mask layer sequentially formed; sequentially etching the hard mask layer, pad oxide layer, and liner form a shallow trench at the bottom; fill the shallow trench with a dielectric, and form a dielectric layer on the substrate surface, the dielectric material can be silicon oxide; anneal the diele...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/762H01L21/265
Inventor 杨芸洪中山
Owner SEMICON MFG INT (SHANGHAI) CORP
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