Apparatus for testing PCIe bus bandwidth and method thereof

A bandwidth and message data technology, applied in digital transmission systems, electrical components, transmission systems, etc., to solve problems such as limited CPU computing power, inability to measure the reliability and stability of PCIe interfaces, and data traffic that cannot reach the maximum bandwidth. , to achieve the effect of saving address calculation time, high accuracy and reducing use cost

Active Publication Date: 2012-04-18
中科腾龙信息技术有限公司
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AI Technical Summary

Problems solved by technology

In the DMA mode, each random length of PCIe packet data needs to be generated by the CPU. Due to the limited computing power of the CPU, the data flow

Method used

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  • Apparatus for testing PCIe bus bandwidth and method thereof

Examples

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Example Embodiment

[0018] like figure 1 As shown, the device for testing PCIe bus bandwidth includes: a memory located in the host device; a message construction module, a DMA write engine module, a DMA read engine module, a message parsing module, and a bandwidth calculation module located in the PCIe device ;

[0019] The device for testing PCIe bus bandwidth constructs a message on the message construction module of the PCIe device, and then uploads the constructed message to the DMA of the host memory through the DMA writing engine module. Write address, the DMA read engine module reads data from the host memory address through the DMA read address of the host memory and transmits the read data to the message parsing module, the message parsing The module submits the length information of the message data to the bandwidth calculation module; finally, the bandwidth calculation module calculates the bandwidth of the message according to the length information of the obtained message data to c...

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Abstract

The invention provides an apparatus for testing PCIe (peripheral component interconnect express) bus bandwidth. The apparatus comprises that: a memory in a host device; a message construction module, a DMA write engine module, a DMA read engine module, a message parsing module, and a bandwidth calculating module in a PCIe device. The invention also provides a method for testing PCIe bus bandwidth. The method is characterized in that: constructing a message in the message construction module of the PCIe device, uploading the constructed message to a host memory address through the DMA write engine module, reading stored message data in the host memory address through the DMA read engine module, and finally based on total byte count and transmission time of the message data, calculating bus bandwidth in the bandwidth calculating module. According to the apparatus and the method of the invention, test efficiency in a DMA mode is raised, and accuracy of a data test result is raised simultaneously.

Description

technical field [0001] The invention relates to the field of computer system testing, in particular to a device and method for testing PCIe bus bandwidth. Background technique [0002] The Peripheral Component Interconnect Express (PCIe) bus is a type of Peripheral Component Interconnect (PCI) bus. The PCIe bus follows the existing PCI bus programming concepts and communication standards, and only needs to modify the physical layer to convert an existing PCI system to a PCIe system without requiring software modifications. The PCIe bus replaces the parallel physical layer signals of the PCI bus with a separate serial physical layer for sending and receiving. The PCIe bus has a faster rate and can replace almost all existing internal buses. The data transmission on the PCIe bus is based on the packet (Packet). The minimum length of the packet is 1 byte. The maximum packet length supported by different devices is different. The maximum packet length defined by the PCIe specif...

Claims

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Application Information

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IPC IPC(8): H04L12/26
Inventor 窦晓光纪奎张磊白宗元张英文李静刘灿
Owner 中科腾龙信息技术有限公司
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