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Processor
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A technology of processors and arithmetic units, applied to instruments, electrical digital data processing, machine execution devices, etc., can solve problems such as unhappiness, slow response to instructions, and inability to guarantee the end of processing, etc.
Active Publication Date: 2015-04-08
PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO LTD
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Abstract
Description
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Problems solved by technology
Therefore, the user feels that the response to the instruction made by the user is slow, and feels unpleasant
[0014] In addition, on the contrary, in order to speed up the response to user instructions, it can be considered that the command flow to which this command belongs is given a higher priority than other command flows (command flows requiring performance guarantees), but if this is the case, for the command flows requiring performance guarantees, There will be no guarantee that processing will be completed within the stipulated time
Method used
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no. 2 Embodiment approach
[0112] Here, the processor 10 a of the second embodiment will be described focusing on differences from the processor 10 of the first embodiment.
[0113] Figure 7 It is a block diagram showing the structure of the processor 10a of the second embodiment.
[0114] The processor 10a is a processor that independently executes N (N is an integer equal to or greater than 2) instruction streams (N threads) simultaneously and independently, and includes an instruction memory 601, an instruction group determination unit 602, and N instruction buffers (the first instruction buffer 603, the second command buffer 604, ..., the Nth command buffer 605), the issued command determination unit 606, the priority determination unit 607, N register files (the first register file 608, the second register file 609, ... , the Nth register file 610), the arithmetic unit group 611, the write-back bus 612, and the priority updating unit 613.
[0115] Here, the command buffers and the register files...
no. 3 Embodiment approach
[0180] Here, the processor 10b of the third embodiment will be described focusing on differences from the processors 10 and 10a of the first and second embodiments.
[0181] Figure 13 It is a block diagram showing the structure of the processor 10b of the third embodiment.
[0182] The processor 10b is a processor that simultaneously and independently executes N (N is an integer greater than or equal to 2) instruction streams (N threads), and includes an instruction memory 1101, an instruction group determination unit 1102, and N instruction buffers (the first instruction buffer device 1103, second command buffer 1104, ..., Nth command buffer 1105), issue command determination unit 1106, priority determination unit 1107, N register files (first register file 1108, second register file 1109, ... , Nth register file 1110), arithmetic unit group 1111, write-back bus 1112, priority updating unit 1113, performance monitoring unit 1114.
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Abstract
A processor including L computing units, L being an integer of 2 or greater, the processor comprising: an instruction buffer including M×Z instruction storage areas each storing one instruction, M instruction streams being input in a state of being distinguished from each other, each of the M instruction streams including Z instructions, M and Z each being an integer of 2 or greater, M×Z being equal to or greater than L; an order information holding unit holding order information that indicates an order of the M×Z instruction storage areas; an extraction unit operable to extract instructions from the M×Z instruction storage areas; and a control unit operable to cause the extraction unit to extract L instructions in executable state from the M×Z instruction storage areas in accordance with the order indicated by the order information, and input the instructions into different ones of the L computing units.
Description
technical field [0001] The present invention relates to a technique for simultaneously realizing performance guarantee for one command stream and high responsiveness for other command streams in a processor that executes a plurality of command streams in parallel. Background technique [0002] In recent years, in order to improve the processing efficiency of media processing such as compressing / expanding digitized video data, audio data, etc., a multi-threaded processor is disclosed in Non-Patent Document 1, which executes a plurality of programs simultaneously. Improve operational efficiency. [0003] In addition, there is Patent Document 1 as a technology using a multi-threaded processor. Patent Document 1 discloses a technique of setting processing priorities for a plurality of command streams (threads), and preferentially processing command streams with higher priority. According to this technique, it is possible to dynamically realize required processing performance i...
Claims
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Application Information
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Patent Type & Authority Patents(China)
IPC IPC(8): G06F9/38G06F9/46G06F9/50
CPCG06F9/3851G06F9/3889
Inventor 森下广之
Owner PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO LTD
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