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Reconfigurable binary arithmetical unit, reconfigurable binary image processing system and basic morphological algorithm implementation method thereof

A binary image and processing system technology, applied in the direction of processor architecture/configuration, etc., can solve the problem of difficult real-time processing of large-resolution video signals, inability to meet performance and flexibility at the same time, poor circuit flexibility and scalability, etc. problem, to achieve the effect of simple structure, fast speed, simple structure and rules

Inactive Publication Date: 2012-05-09
XI AN JIAOTONG UNIV
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Problems solved by technology

ASIC designed circuits have very poor flexibility and scalability
The second type of circuit, its array structure and operation method determine that when this structure performs image processing, the efficiency is low and the speed is slow, and it is difficult to process large-resolution video signals in real time; and the control of this structure is very complicated, not conducive to widespread use
[0004] After the above analysis, it can be seen that the current technology cannot meet the requirements of performance and flexibility when processing large-resolution binary images.

Method used

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  • Reconfigurable binary arithmetical unit, reconfigurable binary image processing system and basic morphological algorithm implementation method thereof
  • Reconfigurable binary arithmetical unit, reconfigurable binary image processing system and basic morphological algorithm implementation method thereof
  • Reconfigurable binary arithmetical unit, reconfigurable binary image processing system and basic morphological algorithm implementation method thereof

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Embodiment Construction

[0037] refer to figure 1 , the basic binary operation unit includes: the first line memory (line memory 1), the second line memory (line memory 2), the fifth multiplexer (MUX5) connected with the first line memory, and the second line memory The sixth multiplexer (MUX6) connected, n groups of binary logical operation units connected with the fifth multiplexer and the sixth multiplexer, the reduction operation unit connected with n groups of binary logical operation units and Median filter unit.

[0038] Wherein the first line is stored and the second line is stored for storing binary image data; the fifth multiplexer and the sixth multiplexer select the input of the logical operation unit; each of the several groups of binary logical operation units includes a Road register, b-way register and binary logic operation unit, the fifth multiplexer is connected with the a-way register of each group of binary logic operation unit to form the a-way of the basic operation unit; the s...

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Abstract

The invention relates to an image processing technology, specifically relates to a binary image processing technology and provides a reconfigurable binary image arithmetical unit structure. The invention has the advantages of simple structure, fewer resources, high speed and easy implantation process. The invention also constructs a binary image processing system based on the structure, and provides a binary image mathematical morphological algorithm implementation method on the binary image processing system. The invention can flexibly realize multiple binary image operations, has the advantages of simple and regular structure and high processing speed, and can process high-resolution binary images in real time.

Description

technical field [0001] The present invention relates to the technical field of binary image processing, in particular to a reconfigurable binary operator for binary image processing, a reconfigurable binary image processing system constructed based on the reconfigurable binary operator and its Methods for implementing basic morphological algorithms. Background technique [0002] Binary images are used in various applications such as shape analysis, feature recognition, and skeletonization in the fields of image processing, pattern recognition, machine vision, and navigation. In particular, the development of mathematical morphology has provided fast algorithms and a complete theoretical system for binary image processing. In this way, the visual algorithm and image processing method based on binary images are simple, easy to implement, and fast in calculation speed, which is very suitable for the use of embedded systems. [0003] Currently existing embedded hardware system...

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Application Information

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IPC IPC(8): G06T1/20
Inventor 张斌梅魁志郑南宁雷浩李宇海董培祥赵晨殷浩
Owner XI AN JIAOTONG UNIV
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