Chip-grade electromagnetic interference shielding structure and manufacturing method thereof
A technology of electromagnetic interference shielding and manufacturing method, which is applied in the direction of semiconductor/solid-state device manufacturing, circuits, electrical components, etc.
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no. 1 example
[0029] figure 1 It is a schematic diagram of a chip-level electromagnetic interference shielding structure according to the first embodiment of the present invention. The chip-level EMI shielding structure mainly includes a semiconductor substrate 110 , a ground layer 111 , a connection structure 112 , a ground wire 121 and a protective layer 140 . There is a redistribution layer (Redistribution Layer, RDL) on the upper surface (first surface) of the semiconductor substrate 110 to connect the chips 131-134, and there are a plurality of metal wires in the redistribution layer, which are used to connect the chips 131-134 or conduct electrical connections. transmission of signals. The ground wire 121 is disposed on the first surface of the semiconductor substrate 110 and located at an edge of the semiconductor substrate 110 . The lower surface (second surface) of the semiconductor substrate 110 has a metal layer on the entire surface, and the metal layer is a ground layer 111 ....
no. 2 example
[0034] In order to realize the above-mentioned chip-level electromagnetic interference shielding structure, the present invention proposes a manufacturing method of a chip-level electromagnetic interference shielding structure, please refer to figure 2 , figure 2 is a schematic diagram of a chip process according to a second embodiment of the present invention. Firstly, the redistribution layer and the ground wire 121 are formed on the semiconductor substrate 110 (or the wafer), and the ground wire 121 is disposed on the edge of the semiconductor substrate 110 . If the ground wire 121 is formed on the wafer, the ground wire 121 will be disposed between different chip placement regions. After the wafer is diced, the ground wire 121 will also be located at the edge of the diced semiconductor substrate 110 . The chips 131 - 134 are disposed on the semiconductor substrate 110 in a flip chip (flip chip) manner (refer to the structure 210 ). Next, a protection layer 140 is forme...
no. 3 example
[0037] Next, the manufacturing method of the chip-level electromagnetic interference shielding structure of the present invention is illustrated with a flow chart, please refer to image 3 and Figure 4 , Figure 4 It is a flow chart of the manufacturing method according to the third embodiment of the present invention. Firstly, a redistribution layer is formed on a first surface of a chip (step S410), and then at least one ground wire 121 is formed on the first surface of the chip (step S420). Next, at least one chip 131 - 134 is disposed on the first surface of the wafer and the ground wire 121 is located between the chips 131 - 134 (step S430 ). Then a ground layer 111 is formed on a second surface of the chip (step S440). Next, a protective layer 140 is formed on the wafer to cover the chips 131-134 (step S450). After the protective layer 140 and metal wires 151, 152 are formed, the wafer is cut into a plurality of semiconductor substrates 110, ground wires 121 are res...
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