Memory device and method of manufacturing the same, memory system and multilayer device
A technology for storage devices and charge storage layers, which is applied in semiconductor/solid-state device manufacturing, semiconductor/solid-state device components, semiconductor devices, etc., and can solve problems such as unrealistic integration of two-dimensional memory devices
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Embodiment 1
[0079] refer to Figure 1A with 1B The semiconductor device 91 may include a plurality of vertical channels 110 provided on a semiconductor substrate 190 , and a plurality of conductive patterns 150 stacked along the extending direction of the vertical channels 110 . In this example embodiment, the conductive pattern 150 includes the gate of the device 91 and constitutes the word line WL and selection lines SSL and GSL of the device. Also shown are a plurality of bit lines 170 electrically connected to the vertical channel 110 .
[0080] Lower portions of the vertical channels 110 may be respectively connected to the semiconductor substrate 190 . The upper portions of the vertical channels 110 of different groups may be respectively connected to the common bit line 170 via the contact pads 172 . The gate 150 of each layer of the device can be commonly formed: a ground selection line GSL, as the conductive layer closest to the semiconductor substrate 190; a string selection l...
Embodiment 2
[0095] refer to Figure 1H , the semiconductor device 91 a may include: a plurality of vertical channels 110 extending in a vertical direction with respect to the semiconductor substrate 190 ; and a gate stack 105 a in which the gates 150 are vertically stacked along the extending direction of the vertical channels 110 . The gate stack 105a may include an etch stop layer 120 having a vertically stacked stepped shape on opposite sides thereof. In one example, the etch stop layer 120 may extend in a horizontal direction substantially in line with the extending direction of the bit line 170, and may extend on opposite sides of the conductive pattern 150 extending in a direction substantially crossing the extending direction of the bit line 170. at the end. In this example embodiment, the etch stop layer 120 covering the gate stack 105a has a stepped structure on both sides of the memory device. Any of the embodiments of the inventive concept shown here can be applied to Figur...
Embodiment 3
[0097] refer to Figure 1I , the semiconductor device 91b may include a gate stack 105b, wherein the gate 150 is stacked on the semiconductor substrate 190 along the extending direction of the vertical channel 110 . In this embodiment, the gate stack 105a may include an etch stop layer 120 having a vertically stacked step shape on one side thereof. In one example, the etch stop layer 120 may extend in a horizontal direction substantially in line with the extending direction of the bit line 170 and may extend in one end of the conductive pattern 150 in a direction substantially crossing the extending direction of the bit line 170 . In this example embodiment, the etch stop layer 120 covering the gate stack 105a has a stepped structure at one side of the memory device. Any of the embodiments of the inventive concept shown here can be applied to Figure 1H The structure of the embodiment.
[0098]
[0099] Figure 1J is an equivalent circuit diagram showing a semiconductor ...
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