Method for testing a scan-based integrated circuit by synthetic broadcaster and compact tool

Abstract

A broadcaster, system, and method for reducing test data volume and test application time in an ATE (automatic test equipment) in a scan-based integrated circuit. The scan-based integrated circuit contains multiple scan chains, each scan chain comprising multiple scan cells coupled in series. The broadcaster is a combinational logic network coupled to an optional virtual scan controller and an optional scan connector. The virtual scan controller controls the operation of the broadcaster. The system transmits virtual scan patterns stored in the ATE and generates broadcast scan patterns through the broadcaster for testing manufacturing faults in the scan-based integrated circuit. The number of scan chains that can be supported by the ATE is significantly increased. Methods are further proposed to reorder scan cells in selected scan chains, to generate the broadcast scan patterns and virtual scan patterns, and to synthesize the broadcaster and a compactor in the scan-based integrated circuit.

Description

[0001] The patent application of the present invention is the international application number PCT / US03 / 00029, the international application date is January 16, 2003, the application number entering the Chinese national phase is 03802114.5, and the name is "Used to transmit scanning in a scanning-based integrated circuit A divisional application of the invention patent application of "Pattern Method and Device". technical field [0002] The present invention relates generally to the fields of logic design and testing utilizing design for test (DFT) techniques. In particular, the present invention relates to the field of logic testing and diagnostics for integrated circuits using scan or build-in-self-test (BIST) techniques. Background technique [0003] As the complexity of integrated circuits increases, it becomes increasingly important to minimize test costs while achieving very high error coverage. Although traditional scan-based approaches for sub-million gate designs h...

AI Technical Summary

Problems solved by technology

While this can be practically implemented with additional hardware overhead, it makes the scan chains have a very large correlation between the data bits of different scan chains, which leads to an input limit that is too strong to obtain very high error coverage for

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