The application provides an array substrate and a display panel. The array substrate comprises a substrate, a common
electrode layer arranged on the substrate and comprising a common
electrode and a plurality of first scan lines extending along a first direction, and a wiring layer arranged on the common
electrode layer and comprising a plurality of second scan lines extending along a second direction intersecting the first direction, each second
scan line being electrically connected with a corresponding first
scan line, the second scan lines being used for transmitting a scan
signal, the potential of the scan
signal comprising a pulse
peak value and a pulse valley value. The common electrode has the pulse valley value, which comprises making the
voltage on the common electrode be the pulse valley value for making a switch
transistor be closed, thereby reducing the
parasitic capacitance between the common electrode and the second scan lines in most working processes of the pixel, and improving the influence of the
coupling effect of the
parasitic capacitance between the wiring in the vertical direction of the
scan line and the common electrode on the pixel on the display of the display panel in the related art.