Control circuit for reading timing sequence

Abstract

An embodiment of the invention provides a control circuit for reading timing sequence, which comprises a reading pre-charge unit, a sensitivity amplifying delay unit, a data latching delay unit, a data output parallel delay unit and a built-in test module. The reading pre-charge unit is used for generating the reading pre-charge timing sequence triggered by an address transmission monitoring signal and sending a pre-charge preparatory signal to the sensitivity amplifying delay unit and the built-in test module. The sensitivity amplifying delay unit is used for providing processing time for a sensitivity amplifying process to a memory chip. The data latching delay unit outputs a data latching preparatory signal to the data output parallel delay unit and the built-in test module. The data output parallel delay unit is used for outputting and reading and capable of enabling the preparatory signal to be sent to the built-in test module. The built-in test module comprises a dynamic test sub-module with the pre-charge function and is used for outputting a sensitivity amplifying pre-charge signal and a data latching pulse control signal and reading a period enable signal.

Description

technical field [0001] The invention relates to a fast-test reading sequence control circuit. Background technique [0002] The read timing control circuit generates a global read timing control signal for the memory chip, works under the trigger of the address transmission monitoring signal (ATD), and is used to output control signals such as enable, precharge and latch. Testing the read function of the memory chip can be realized through the built-in test module in the read timing control circuit. [0003] The test sequence of the traditional memory chip reading function usually adopts static excitation, which lacks control over the dynamic transition process of the internal circuit of the memory, which makes the test efficiency insufficient and the test speed slow. Contents of the invention [0004] In view of this, the object of the present invention is to provide a read timing control circuit, which can improve the speed of memory read function test. [0005] To ach...

AI Technical Summary

Problems solved by technology

[0003] The test sequence of the traditional memory chip reading function usually adopts static excitation, which lacks control over the dynamic transition process of the internal circuit of the memory, which makes the test efficiency insufficient and the test speed slow

Images