Method for realizing interrupted load balance among multi-core processors

A multi-core processor, load balancing technology, applied in the field of computer networks, can solve the problems of inability to run key real-time tasks, heavy interrupt load, loss of low-priority interrupts, etc., to achieve good practicability, improve parallelism, and improve processing efficiency. Effect

Active Publication Date: 2014-07-09
CHONGQING UNIV OF POSTS & TELECOMM
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Problems solved by technology

[0006] The present invention only statically allocates device interrupts to the corresponding processor cores in the existing interrupt load balancing technology, and high-priority interrupts are processed too frequently on a certain processor core, which will cause low-priority interrupts to be lost , or because the interrupt load of a certain processor core is too heavy, resulting in some technical problems such as the inability to run some key real-time tasks, the present invention provides a method for implementing interrupt load balancing among multi-core processors in a high-speed network traffic monitoring system

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  • Method for realizing interrupted load balance among multi-core processors
  • Method for realizing interrupted load balance among multi-core processors
  • Method for realizing interrupted load balance among multi-core processors

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Embodiment Construction

[0025] During high-speed network traffic monitoring, the network transmits more than three million data packets per second. For the monitoring system, that is, at least three million interrupts (including hard interrupts and soft interrupts) will be generated per second. The monitoring system based on the SMP platform must distribute these interrupts to each processor in a balanced manner, respond and process them synchronously and in parallel, in order to achieve efficient work of the system.

[0026] The present invention is a kind of interrupt load balancing realization method among multi-core processors in the high-speed network flow monitoring system, combined below figure 1 Describe its specific implementation process.

[0027] 1. Create a dispatch domain. A scheduling domain is a collection of processor cores whose interrupt load needs to be balanced. For processor cores sharing a secondary cache, it is a prerequisite for building a scheduling domain. Divide the pro...

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Abstract

The invention relates to a method for realizing interrupted load balance among multi-core processors, belonging to the computer network technology. The technical scheme adopted by the balancing method of the invention is as follows: dividing processors sharing a second level cache to the same scheduling region, distributing all data packets to each scheduling region according to source IP addresses, establishing a hash table, and carrying out analytical statistics on the data packets, wherein each scheduling region can have a critical access to respective hash table; and adopting a weighted cycle scheduling algorithm to realize the load balance in each scheduling region, allocating the interruption sent by a network card to each processor, and setting a server priority according to weight values, wherein the server with a higher weight value preferentially receives and processes the interruption, and the processors with the same weight values process the interruption in a cycle scheduling manner. Since an operating system can balance the interrupted load, the interruption sent by the network card can be subjected to balanced distribution on the multiple processor cores, thus the processing efficiency of the system can be improved.

Description

technical field [0001] The invention relates to computer network technology, in particular to the multi-core processor operating system technology of a high-speed network flow monitoring system. Background technique [0002] In the process of high-speed network traffic monitoring, the system will receive massive data packets every second, and analyze and process them, involving data collection, data analysis, data storage, etc. The system generally uses a high-performance multi-core hardware platform to efficiently receive and process network packet packets in parallel. In a multi-core processor environment, if all interrupts are processed on a certain processor core, high-priority interrupts are processed too frequently on a certain processor core, which will cause low-priority interrupts to be lost, or due to a certain processing The interrupt load of the processor core is too heavy, which makes some key real-time tasks unable to run. [0003] A "multi-core processor int...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F9/50
Inventor 徐川唐红赵国锋张毅
Owner CHONGQING UNIV OF POSTS & TELECOMM
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