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Test mode controller and electronic device with self-testing function

A technology of test mode and controller, which is applied in the direction of measuring device, electrical test/monitoring, electrical measurement, etc., can solve the problems of test pin TD empty connection, increase packaging cost, waste chip area, etc., and achieve low packaging cost and shorten The effect of small test time and chip area

Inactive Publication Date: 2012-07-04
FORTUNE SEMICON
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, when the single-cell lithium battery protection chip 11 operates in the normal mode, the test pin TD will be disconnected
[0005] To sum up, the traditional single-cell lithium battery protection chip 11 may waste chip area and increase packaging cost due to the extra test pin TD
Similarly, traditional chips may also require additional test pins, and may have the same problem

Method used

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  • Test mode controller and electronic device with self-testing function
  • Test mode controller and electronic device with self-testing function
  • Test mode controller and electronic device with self-testing function

Examples

Experimental program
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Embodiment Construction

[0060] Example of a test mode controller

[0061] Please refer to figure 2 , figure 2 It is a circuit diagram of a test mode controller provided by an embodiment of the present invention. The test mode controller 2 includes an enable signal generator 22 , a control signal generator 21 and a latch 23 . The control signal generator 21 is electrically coupled to the enable signal generator 22 and the latch 23 , and the latch 23 is electrically coupled to the enable signal generator 22 .

[0062] The enable signal generator 22 receives the second control signal Ds_c and the power signal VDD from the latch 23, and generates a first enable signal En_cmp and a second enable signal En_Latch, wherein the first enable signal En_cmp and the second enable signal The two enable signals En_latch are sent to the latch 23 and the control signal generator 21 respectively. The enabling and disabling time of the first enable signal En_cmp will be image 3 or Figure 6 Note that, similarl...

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PUM

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Abstract

The invention relates to a test mode controller and an electronic device with self-testing function. The test mode controller comprises an enabling signal generator, a control signal generator and a latch. The enabling signal generator is used for receiving a power supply signal and a second control signal, generating a first enabling signal and a second enabling respectively for the first enabling signal and the second enabling signal; the control signal generator is used for receiving a power supply indicating voltage and a reference voltage, and generating a first control signal and transmitting the first control signal to the latch when the first enabling signal enables; and the latch is used for receiving the first control signal when the second enabling signal enables and generating a second control signal according to the first control signal, wherein the second control signal is used for controlling a chip to operate in a first test mode or a common mode. Therefore, the test mode controller does not need to use a test connection pin, the testing time can be shortened, and the chip area and the packaging cost can be saved.

Description

technical field [0001] The present invention relates to an electronic device with self-test, and more particularly to a test mode controller for the self-test electronic device. Background technique [0002] Currently, the widely used electronic circuits on the market are implemented on a single chip in the form of an integrated circuit. When producing a chip, in addition to considering the efficiency, the usage area of ​​the chip and the packaging cost required according to the number of pins are also considered. Accordingly, most manufacturers will also devote themselves to reducing the chip area and the number of pins when producing chips. [0003] The following takes a traditional single-cell lithium battery protection circuit as an example to illustrate that traditional chips require additional test pins to shorten the test time of traditional chips. Please refer to figure 1 , figure 1 It is a circuit diagram of a traditional single-cell lithium battery protection c...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G05B23/02
CPCG01R31/31724
Inventor 陈国强陈宴毅
Owner FORTUNE SEMICON
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