System and method for improving direct memory access (DMA) efficiency of multi-data buffer

A data buffer and buffer technology, applied in the field of digital information transmission, can solve problems such as unsolved descriptor time overhead and system bus overhead, and multiple data buffer overheads are not considered, so as to improve utilization and message transmission. Speed, improved DMA efficiency, resolution time overhead and effects of large system bus overhead

Active Publication Date: 2012-07-04
DAWNING INFORMATION IND BEIJING +1
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  • Application Information

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Problems solved by technology

[0006] The above inventions and papers are the optimization and extension of the traditional descriptor mechanism, and do not solve the time overhead and system bus overhead caused by descriptor transmission; and the overhead caused by the management of multiple data buffers in the operating system also did not consider

Method used

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  • System and method for improving direct memory access (DMA) efficiency of multi-data buffer
  • System and method for improving direct memory access (DMA) efficiency of multi-data buffer
  • System and method for improving direct memory access (DMA) efficiency of multi-data buffer

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Embodiment Construction

[0031] figure 1 This is the overall structure diagram of the system. A system for improving the DMA efficiency of multiple data buffers, comprising: a host and a network card connected to it through an IO bus, the host comprising: a data buffer, a data buffer information module and a DMA controller, characterized in that the The network card includes: a data buffer information management unit and a DMA request queue and a return data receiving queue communicating respectively with the DMA controller; the data buffer information (Buffer Info) in the data buffer information module is transmitted to all The above data buffer information management unit.

[0032] The number of the DMA request queue and the number of the return data receiving queue are 4; the number of the data buffers is 64. The data buffer information management unit includes: Buffer Info module, Lock module, Buffer Number module 1, Block Address module, Block Length module, DMA Info Available module and Ack fo...

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Abstract

The invention provides a system and a method for improving direct memory access (DMA) efficiency of a multi-data buffer. The method comprises (1) when an application program fills data into the data buffer, relevant information of the buffer is transmitted to a network card through a host machine input/output (IO) bus and is stored in an information management module of the data buffer; (2) when detecting that data in the data buffer need to be transmitted, the information management module of the data buffer extracts addresses and lengths of the data waiting for being transmitted from the relevant information of the buffer and transmits the addresses and the lengths of the data to a DMA request queue; (3) DMA request queue organizes requests of data blocks into one or more DMA requests meeting requirements of the host machine IO bus and transmits the DMA requests to a host machine; and (4) a DMA controller of the host machine responds received DMA requests and transmits requested data to the network card through the host machine IO bus. The system and the method for improving the DMA efficiency of the multi-data buffer are based on a multi-queue DMA engine in a non-descriptor mechanism and improve utilization rate and message transmission speed of the host machine IO bus.

Description

technical field [0001] The invention belongs to the field of digital information transmission, and in particular relates to a system and method for improving DMA efficiency of multiple data buffers. Background technique [0002] In the prior art, it takes a long time from requesting data from the network card to returning the data from the memory of the host. In a single-queue DMA system, the host IO bus is always idle during the period from request sending to data return, which wastes a lot of bus bandwidth. This phenomenon is more serious in a descriptor mechanism system using interrupts. At the same time, the existing network card does not consider supporting the data buffers of multiple applications. For servers running on high-speed networks, the management of multiple data buffers by the operating system will occupy a considerable amount of CPU resources, thereby affecting Efficiency in the use of the host IO bus. [0003] Patent No.: ZL200680011384.0, PCT titled "Co...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F13/28
Inventor 李旭窦晓光张磊纪奎李静白宗元张英文
Owner DAWNING INFORMATION IND BEIJING
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